Optimized read current consumption based on lower page read information for non-volatile memory apparatus
A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells retain a threshold voltage corresponding to data states. A control means applies a bit line voltage to the bit lines while determining whether the memory cells have the threshold voltage above one or more read levels associated with each of the data states in a first portion of a read operation. The control means groups the memory cells targeted for ones of the data states into data state groups based on the first portion of the read operation. The control means also supplies a near zero voltage to the bit lines coupled to the memory cells targeted for ones of the data states associated with at least one of the data state groups while reading the memory cells in subsequent portions of the read operation.
1. A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in memory holes each connected to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means coupled to the plurality of word lines and the plurality of bit lines and configured to:
apply a bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in a first portion of a read operation,
group the memory cells targeted for ones of the plurality of data states into a plurality of data state groups based on the first portion of the read operation, and
supply a near zero voltage to the plurality of bit lines coupled to the memory cells targeted for ones of the plurality of data states associated with at least one of the plurality of data state groups while reading the memory cells targeted for one or more of the plurality of data states in subsequent portions of the read operation.
2. The memory apparatus as set forth in claim 1 , wherein the memory cells comprise a plurality of pages each storing a plurality of bits of data stored in the memory apparatus, the plurality of bits including a lower bit associated with a lower page of the plurality of pages, the one or more of the plurality of read levels associated with each of the plurality of data states in the first portion of the read operation including the plurality of read levels corresponding to the plurality of data states used to discern the lower bit of each of the memory cells, and the control means is further configured to:
read the memory cells to determine whether the memory cells have the threshold voltage above the plurality of read levels corresponding to the plurality of data states used to discern the lower bit of each of the memory cells in the first portion of the read operation; and
read the memory cells to determine whether the memory cells have the threshold voltage above the plurality of read levels corresponding to the plurality of data states used to discern the plurality of bits of the data of each of the memory cells other than the lower bit in the subsequent portions of the read operation.
3. The memory apparatus as set forth in claim 2 , wherein the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased state, a plurality of programmed data states, the memory apparatus further includes a plurality of data state latches including a lower bit latch configured to store the lower bit for the lower page of the data, and the control means is further configured to:
group the memory cells targeted for ones of the plurality of data states into the plurality of data state groups based on the lower bit latch;
apply the bit line voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a zero while reading the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a zero in the subsequent portions of the read operation; and
supply the near zero voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a one while reading the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a one in the subsequent portions of the read operation.
4. The memory apparatus as set forth in claim 3 , wherein the plurality of bits further includes a middle bit associated with a middle page of the plurality of pages and an upper bit associated with an upper page of the plurality of pages, the plurality of data state latches includes a trip latch coupled to the plurality of data state latches and a voltage clamp configured to set the bit line voltage at a sense node and a cache configured to store one bit of the data from the control means, the first portion of the read operation includes a lower page read to determine the lower bit of the memory cells and the subsequent portions of the read operation include a middle page read to determine the middle bit of the memory cells and an upper page read to determine the upper bit of the memory cells, and the control means is further configured to:
set the trip latch equal to one, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the trip latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node, and set the cache equal to the trip latch in the lower page read;
set the trip latch equal to the lower bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the trip latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch equal to not the sense node, and set the cache equal to the trip latch in the middle page read; and
set the trip latch equal to the lower bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the trip latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node, and set the cache equal to the trip latch in the upper page read.
5. The memory apparatus as set forth in claim 2 , wherein the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased state, a plurality of programmed data states, the plurality of data states grouped into a plurality of data state groups including, in order of the threshold voltage increasing in magnitude, an erased data state group and a first programmed data state group and a second programmed data state group, the erased data state group comprising the erased state, and the control means is further configured to:
group the memory cells targeted for ones of the plurality of data states into the plurality of data state groups based on relative magnitudes of the threshold voltage;
supply the near zero voltage to the plurality of bit lines coupled to the memory cells targeted for the erased data state group while reading the memory cells in the subsequent portions of the read operation;
apply the bit line voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states in the first programmed data state group and the second programmed data state group while reading the memory cells targeted for each of the plurality of data states in the first programmed data state group in the subsequent portions of the read operation; and
supply the near zero voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states in the first programmed data state group while reading the memory cells targeted for each of the plurality of data states in the second programmed data state group in the subsequent portions of the read operation.
6. The memory apparatus as set forth in claim 5 , wherein the plurality of bits further includes a middle bit associated with a middle page of the plurality of pages and an upper bit associated with an upper page of the plurality of pages, the memory apparatus further includes a plurality of data state latches including a lower bit latch configured to store the lower bit for the lower page of the data and a middle bit latch configured to store the middle bit for the middle page of the data and an upper bit latch configured to store the upper bit for the upper page of the data and a trip latch coupled to the plurality of data state latches and a voltage clamp configured to set the bit line voltage at a sense node and a cache configured to store one bit of the data from the control means, the first portion of the read operation includes a lower page read to determine the lower bit of the memory cells and the subsequent portions of the read operation include a middle page read to determine the middle bit of the memory cells and an upper page read to determine the upper bit of the memory cells, and the control means is further configured to:
set the trip latch equal to one, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the trip latch, set the trip latch equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to or less than the sense node, and set the trip latch equal to the lower bit latch logically anded with the sense node in the lower page read;
set the trip latch equal to logically not the lower bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the middle bit latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node logically anded with the middle bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch equal to not the sense node, and set the cache equal to the trip latch in the middle page read; and
set the trip latch equal to logically not the lower bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the middle bit latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node, and set the cache equal to the trip latch in the upper page read.
7. The memory apparatus as set forth in claim 1 , wherein the read operation is a reverse order read.
8. A controller in communication with a memory apparatus including memory cells each connected to one of a plurality of word lines and disposed in memory holes each connected to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the controller configured to:
instruct the memory apparatus to apply a bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in a first portion of a read operation;
group the memory cells targeted for ones of the plurality of data states into a plurality of data state groups based on the first portion of the read operation; and
instruct the memory apparatus to supply a near zero voltage to the plurality of bit lines coupled to the memory cells targeted for ones of the plurality of data states associated with at least one of the plurality of data state groups while reading the memory cells targeted for one or more of the plurality of data states in subsequent portions of the read operation.
9. The controller as set forth in claim 8 , wherein the memory cells comprise a plurality of pages each storing a plurality of bits of data stored in the memory apparatus, the plurality of bits including a lower bit associated with a lower page of the plurality of pages, the one or more of the plurality of read levels associated with each of the plurality of data states in the first portion of the read operation including the plurality of read levels corresponding to the plurality of data states used to discern the lower bit of each of the memory cells, and the controller is further configured to:
instruct the memory apparatus to read the memory cells to determine whether the memory cells have the threshold voltage above the plurality of read levels corresponding to the plurality of data states used to discern the lower bit of each of the memory cells in the first portion of the read operation; and
instruct the memory apparatus to read the memory cells to determine whether the memory cells have the threshold voltage above the plurality of read levels corresponding to the plurality of data states used to discern the plurality of bits of the data of each of the memory cells other than the lower bit in the subsequent portions of the read operation.
10. The controller as set forth in claim 9 , wherein the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased state, a plurality of programmed data states, the memory apparatus further includes a plurality of data state latches including a lower bit latch configured to store the lower bit for the lower page of the data, and the controller is further configured to:
group the memory cells targeted for ones of the plurality of data states into the plurality of data state groups based on the lower bit latch;
instruct the memory apparatus to apply the bit line voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a zero while reading the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a zero in the subsequent portions of the read operation; and
instruct the memory apparatus to supply the near zero voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a one while reading the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a one in the subsequent portions of the read operation.
11. The controller as set forth in claim 10 , wherein the plurality of bits further includes a middle bit associated with a middle page of the plurality of pages and an upper bit associated with an upper page of the plurality of pages, the plurality of data state latches includes a trip latch coupled to the plurality of data state latches and a voltage clamp configured to set the bit line voltage at a sense node and a cache configured to store one bit of the data from the controller, the first portion of the read operation includes a lower page read to determine the lower bit of the memory cells and the subsequent portions of the read operation include a middle page read to determine the middle bit of the memory cells and an upper page read to determine the upper bit of the memory cells, and the controller is further configured to:
instruct the memory apparatus to set the trip latch equal to one, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the trip latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node, and set the cache equal to the trip latch in the lower page read;
instruct the memory apparatus to set the trip latch equal to the lower bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the trip latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch equal to not the sense node, and set the cache equal to the trip latch in the middle page read; and
instruct the memory apparatus to set the trip latch equal to the lower bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the trip latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node, and set the cache equal to the trip latch in the upper page read.
12. The controller as set forth in claim 9 , wherein the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased state, a plurality of programmed data states, the plurality of data states grouped into a plurality of data state groups including, in order of the threshold voltage increasing in magnitude, an erased data state group and a first programmed data state group and a second programmed data state group, the erased data state group comprising the erased state, and the controller is further configured to:
group the memory cells targeted for ones of the plurality of data states into the plurality of data state groups based on relative magnitudes of the threshold voltage;
instruct the memory apparatus to supply the near zero voltage to the plurality of bit lines coupled to the memory cells targeted for the erased data state group while reading the memory cells in the subsequent portions of the read operation;
instruct the memory apparatus to apply the bit line voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states in the first programmed data state group and the second programmed data state group while reading the memory cells targeted for each of the plurality of data states in the first programmed data state group in the subsequent portions of the read operation; and
instruct the memory apparatus to supply the near zero voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states in the first programmed data state group while reading the memory cells targeted for each of the plurality of data states in the second programmed data state group in the subsequent portions of the read operation.
13. The controller as set forth in claim 12 , wherein the plurality of bits further includes a middle bit associated with a middle page of the plurality of pages and an upper bit associated with an upper page of the plurality of pages, the memory apparatus further includes a plurality of data state latches including a lower bit latch configured to store the lower bit for the lower page of the data and a middle bit latch configured to store the middle bit for the middle page of the data and an upper bit latch configured to store the upper bit for the upper page of the data and a trip latch coupled to the plurality of data state latches and a voltage clamp configured to set the bit line voltage at a sense node and a cache configured to store one bit of the data from the controller, the first portion of the read operation includes a lower page read to determine the lower bit of the memory cells and the subsequent portions of the read operation include a middle page read to determine the middle bit of the memory cells and an upper page read to determine the upper bit of the memory cells, and the controller is further configured to:
instruct the memory apparatus to set the trip latch equal to one, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the trip latch, set the trip latch equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to or less than the sense node, and set the trip latch equal to the lower bit latch logically anded with the sense node in the lower page read;
instruct the memory apparatus to set the trip latch equal to logically not the lower bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the middle bit latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node logically anded with the middle bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch equal to not the sense node, and set the cache equal to the trip latch in the middle page read; and
instruct the memory apparatus to set the trip latch equal to logically not the lower bit latch, set the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, set the trip latch to be logically not the sense node logically anded with the middle bit latch, set the sense node equal to one, set the sense node to equal to the sense node logically anded with the trip latch, set the trip latch equal to logically not the sense node, and set the cache equal to the trip latch in the upper page read.
14. A method of operating a memory apparatus including memory cells each connected to one of a plurality of word lines and disposed in memory holes each connected to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the method comprising the steps of:
applying a bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in a first portion of a read operation;
grouping the memory cells targeted for ones of the plurality of data states into a plurality of data state groups based on the first portion of the read operation; and
supplying a near zero voltage to the plurality of bit lines coupled to the memory cells targeted for ones of the plurality of data states associated with at least one of the plurality of data state groups while reading the memory cells targeted for one or more of the plurality of data states in subsequent portions of the read operation.
15. The method as set forth in claim 14 , wherein the memory cells comprise a plurality of pages each storing a plurality of bits of data stored in the memory apparatus, the plurality of bits including a lower bit associated with a lower page of the plurality of pages, the one or more of the plurality of read levels associated with each of the plurality of data states in the first portion of the read operation including the plurality of read levels corresponding to the plurality of data states used to discern the lower bit of each of the memory cells, and the method further includes the steps of:
reading the memory cells to determine whether the memory cells have the threshold voltage above the plurality of read levels corresponding to the plurality of data states used to discern the lower bit of each of the memory cells in the first portion of the read operation; and
reading the memory cells to determine whether the memory cells have the threshold voltage above the plurality of read levels corresponding to the plurality of data states used to discern the plurality of bits of the data of each of the memory cells other than the lower bit in the subsequent portions of the read operation.
16. The method as set forth in claim 15 , wherein the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased state, a plurality of programmed data states, the memory apparatus further includes a plurality of data state latches including a lower bit latch configured to store the lower bit for the lower page of the data, and the method further includes the steps of:
grouping the memory cells targeted for ones of the plurality of data states into the plurality of data state groups based on the lower bit latch;
applying the bit line voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a zero while reading the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a zero in the subsequent portions of the read operation; and
supplying the near zero voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a one while reading the memory cells targeted for each of the plurality of data states corresponding to the lower bit latch storing a one in the subsequent portions of the read operation.
17. The method as set forth in claim 16 , wherein the plurality of bits further includes a middle bit associated with a middle page of the plurality of pages and an upper bit associated with an upper page of the plurality of pages, the plurality of data state latches includes a trip latch coupled to the plurality of data state latches and a voltage clamp configured to set the bit line voltage at a sense node and a cache configured to store one bit of the data, the first portion of the read operation includes a lower page read to determine the lower bit of the memory cells and the subsequent portions of the read operation include a middle page read to determine the middle bit of the memory cells and an upper page read to determine the upper bit of the memory cells, and the method further includes the steps of:
setting the trip latch equal to one, setting the sense node equal to one, setting the sense node equal to the sense node logically anded with the trip latch, setting the trip latch to be logically not the sense node logically anded with the trip latch, setting the sense node equal to one, setting the sense node to equal to the sense node logically anded with the trip latch, setting the trip latch equal to logically not the sense node, and setting the cache equal to the trip latch in the lower page read;
setting the trip latch equal to the lower bit latch, setting the sense node equal to one, setting the sense node equal to the sense node logically anded with the trip latch, setting the trip latch to be logically not the sense node logically anded with the trip latch, setting the sense node equal to one, setting the sense node to equal to the sense node logically anded with the trip latch, setting the trip latch equal to logically not the sense node, setting the sense node equal to one, set the sense node equal to the sense node logically anded with the trip latch, setting the trip latch equal to not the sense node, and setting the cache equal to the trip latch in the middle page read; and
setting the trip latch equal to the lower bit latch, setting the sense node equal to one, setting the sense node equal to the sense node logically anded with the trip latch, setting the trip latch to be logically not the sense node logically anded with the trip latch, setting the sense node equal to one, setting the sense node to equal to the sense node logically anded with the trip latch, setting the trip latch equal to logically not the sense node, and setting the cache equal to the trip latch in the upper page read.
18. The method as set forth in claim 15 , wherein the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased state, a plurality of programmed data states, the plurality of data states grouped into a plurality of data state groups including, in order of the threshold voltage increasing in magnitude, an erased data state group and a first programmed data state group and a second programmed data state group, the erased data state group comprising the erased state, and the method further includes the steps of:
grouping the memory cells targeted for ones of the plurality of data states into the plurality of data state groups based on relative magnitudes of the threshold voltage;
supplying the near zero voltage to the plurality of bit lines coupled to the memory cells targeted for the erased data state group while reading the memory cells in the subsequent portions of the read operation;
applying the bit line voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states in the first programmed data state group and the second programmed data state group while reading the memory cells targeted for each of the plurality of data states in the first programmed data state group in the subsequent portions of the read operation; and
supplying the near zero voltage to the plurality of bit lines coupled to the memory cells targeted for each of the plurality of data states in the first programmed data state group while reading the memory cells targeted for each of the plurality of data states in the second programmed data state group in the subsequent portions of the read operation.
19. The method as set forth in claim 18 , wherein the plurality of bits further includes a middle bit associated with a middle page of the plurality of pages and an upper bit associated with an upper page of the plurality of pages, the memory apparatus further includes a plurality of data state latches including a lower bit latch configured to store the lower bit for the lower page of the data and a middle bit latch configured to store the middle bit for the middle page of the data and an upper bit latch configured to store the upper bit for the upper page of the data and a trip latch coupled to the plurality of data state latches and a voltage clamp configured to set the bit line voltage at a sense node and a cache configured to store one bit of the data, the first portion of the read operation includes a lower page read to determine the lower bit of the memory cells and the subsequent portions of the read operation include a middle page read to determine the middle bit of the memory cells and an upper page read to determine the upper bit of the memory cells, and method further includes the steps of:
setting the trip latch equal to one, setting the sense node equal to one, setting the sense node equal to the sense node logically anded with the trip latch, setting the trip latch to be logically not the sense node logically anded with the trip latch, setting the trip latch equal to one, setting the sense node to equal to the sense node logically anded with the trip latch, setting the trip latch equal to or less than the sense node, and setting the trip latch equal to the lower bit latch logically anded with the sense node in the lower page read;
setting the trip latch equal to logically not the lower bit latch, setting the sense node equal to one, setting the sense node equal to the sense node logically anded with the trip latch, setting the trip latch to be logically not the sense node logically anded with the middle bit latch, setting the sense node equal to one, setting the sense node to equal to the sense node logically anded with the trip latch, setting the trip latch equal to logically not the sense node logically anded with the middle bit latch, setting the sense node equal to one, setting the sense node equal to the sense node logically anded with the trip latch, setting the trip latch equal to not the sense node, and setting the cache equal to the trip latch in the middle page read; and
setting the trip latch equal to logically not the lower bit latch, setting the sense node equal to one, setting the sense node equal to the sense node logically anded with the trip latch, setting the trip latch to be logically not the sense node logically anded with the middle bit latch, setting the sense node equal to one, setting the sense node to equal to the sense node logically anded with the trip latch, setting the trip latch equal to logically not the sense node, and setting the cache equal to the trip latch in the upper page read.
20. The method as set forth in claim 14 , wherein the read operation is a reverse order read.