Programming techniques that utilize analog bitscan in a memory device
The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program at least some of the plurality of memory cells of a selected word line of the plurality of word lines in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is also configured to determine an output of the analog bitscan operation. The output is one of at least three options. The circuitry is further configured to control at least one programming parameter based on the output of the analog bitscan operation.
1 . A method of performing a programming operation in a memory device, comprising the steps of:
preparing a memory block that includes a plurality of memory cells that are arranged in a plurality of word lines, the plurality of word lines including a selected word line;
programming at least some of the plurality of memory cells to at least three bits of data per memory cell in at least one program loop that includes a programming pulse, a verify operation, and an analog bitscan operation, the at least three bits of data per memory cell being associated with a plurality of data states that are associated with respective threshold voltage ranges;
determining an output of the analog bitscan operation, the output being one of at least three options;
determining that programming has completed for a second-to-last data state of the plurality of data states; and
determining a maximum number of additional program loops to perform before ending the programming operation for the selected word line based on the output of the analog bitscan operation.
2 . The method as set forth in claim 1 , wherein the at least three options for the output of the analog bitscan operation comprise pass, weak fail, and strong fail.
3 . The method as set forth in claim 1 , wherein the at least three options for the output of the analog bitscan operation comprise strong pass, weak pass, weak fail, and strong fail.
4 . The method as set forth in claim 3 , wherein in response to the output of the analog bitscan operation being a weak pass, the maximum number of additional program loops to perform before ending the programming operation for the selected word line is set at a first number of program loops;
in response to the output of the analog bitscan operation being a strong pass, the maximum number of additional program loops to perform before ending the programming operation for the selected word line is set at a second number of program loops; and
wherein the first number of program loops is greater than the second number of program loops.
5 . The method as set forth in claim 4 , wherein between program loops, a voltage of the programming pulse increases by a step size and
wherein between the additional program loops, a magnitude of the step size is set as a function of the output of the analog bitscan operation.
6 . A memory device, comprising:
a memory block including a plurality of memory cells that are arranged in a plurality of word lines;
circuitry that is configured to program at least some of the plurality of memory cells of a selected word line of the plurality of word lines to at least three bits of data per memory cell in at least one program loop of a programming operation, the at least three bits of data per memory cell being associated with a plurality of data states that are associated with respective threshold voltage ranges, during the at least one program loop, the circuitry being configured to;
apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation,
determine an output of the analog bitscan operation, the output being one of at least three options,
determine that programming has completed for a second-to-last data state of the plurality of data states; and
determine a maximum number of additional program loops to perform before ending the programming operation for the selected word line based on the output of the analog bitscan operation.
7 . The memory device as set forth in claim 6 , wherein the at least three options for the output of the analog bitscan operation comprise pass, weak fail, and strong fail.
8 . The memory device as set forth in claim 6 , wherein the at least three options for the output of the analog bitscan operation comprise strong pass, weak pass, weak fail, and strong fail.
9 . The memory device as set forth in claim 8 , wherein in response to the output of the analog bitscan operation being a weak pass, the maximum number of additional program loops to perform before ending the programming operation for the selected word line is set at a first number of program loops;
in response to the output of the analog bitscan operation being a strong pass, the maximum number of additional program loops to perform before ending the programming operation for the selected word line is set at a second number of program loops; and
wherein the first number of program loops is greater than the second number of program loops.
10 . The memory device as set forth in claim 9 , wherein between program loops, the circuitry increases a voltage of the programming pulse by a step size and
wherein between the additional program loops, the circuitry sets a magnitude of the step size as a function of the output of the analog bitscan operation.
11 . An apparatus, comprising:
a memory block including a plurality of memory cells that are arranged in a plurality of word lines;
a programming means for programming at least some of the plurality of memory cells of a selected word line of the plurality of word lines to at least three bits of data per memory cell in at least one program loop of a programming operation, the at least three bits of data per memory cell being associated with a plurality of data states that are associated with respective threshold voltage ranges, during the at least one program loop, the programming means being configured to;
apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation,
determine an output of the analog bitscan operation, the output being one of at least three options,
determine that programming has completed for a second-to-last data state of the plurality of data states, and
determine a maximum number of additional program loops to perform before ending the programming operation for the selected word line based on the output of the analog bitscan operation.
12 . The apparatus as set forth in claim 11 , wherein when controlling the at least one programming parameter based on the output of the analog bitscan operation, the programming means is configured to:
in response to the output of the analog bitscan operation being a strong fail, perform an additional program loop with another programming pulse, another verify operation, and another analog bitscan operation;
in response to the output of the analog bitscan operation being a weak fail, perform an additional program loop with another programming pulse, no verify operation, and no analog bitscan operation; and
in response to the output of the analog bitscan operation being a pass, end the programming operation for the selected word line.
13 . The apparatus as set forth in claim 11 , wherein the at least three options for the output of the analog bitscan operation comprise strong pass, weak pass, weak fail, and strong fail.