Post-program erase in 3D NAND
Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.
1 . An apparatus comprising:
one or more control circuits configured to connect to a three-dimensional memory structure comprising blocks, each block having a stack of alternating dielectric layers and conductive layers, each block having NAND strings extending through the alternating dielectric layers and conductive layers, the conductive layers including word lines and a drain side select layer, each NAND string having memory cells and a drain side select transistor, for each block each word line connects to one memory cell on each NAND string in the block, each block divided into sub-blocks with each sub-block having a group of the NAND strings, each sub-block in a particular block having a drain side select line in the drain side select layer of the particular block, wherein for each sub-block the drain side select line connects to the drain side select transistor on each NAND string in the sub-block, the three-dimensional memory structure having bit lines associated with the NAND strings in the blocks, wherein the one or more control circuits are configured to:
erase the memory cells in a selected block to an erase state associated with an erase threshold voltage, including apply a first erase voltage pulse to the bit lines associated with the NAND strings of the selected block while applying a voltage to the drain side select lines of the selected block to create gate-induced drain leakage (GIDL) currents in the NAND strings of the selected block and while applying a non-negative erase enable voltage to the word lines of the selected block;
program a first group of memory cells on a selected word line in a selected sub-block of the selected block from the erase state to target data states associated with corresponding target threshold voltages, including inhibiting a second group of memory cells on the selected word line in the selected sub-block from programming from the erase state and inhibiting a third group of memory cells on the selected word line in unselected sub-blocks in the selected block from programming, the first group of memory cells residing on a first group of the NAND strings in the selected sub-block, the second group of memory cells residing on a second group of the NAND strings in the selected sub-block, the third group of memory cells residing on a third group of NAND strings in the unselected sub-blocks; and
apply erase conditions to the second group of the memory cells in the selected sub-block while inhibiting erase of all other memory cells in the selected block following programming the first group of the memory cells to lower the threshold voltage of memory cells in the second group without regard to whether a pre-erase condition threshold voltage of respective memory cells in the second group are above or below the erase threshold voltage, including apply a second erase voltage pulse to selected bit lines associated with the second group of the NAND strings in the selected sub-block while applying a GIDL voltage to the drain side select line of the selected sub-block to create GIDL currents in the second group of the NAND strings and while applying the non-negative erase enable voltage to the selected word line, wherein inhibiting erase of all other memory cells in the selected block includes applying a voltage that is less than a magnitude of the second erase voltage pulse to unselected bit lines associated with the first group of NAND strings while applying a voltage greater than the GIDL voltage to unselected drain side select lines of the unselected sub-blocks, wherein a first plurality of the NAND strings in the unselected sub-blocks are associated with the selected bit lines and a second plurality of the NAND strings in the unselected sub-blocks are associated with the unselected bit lines.
2 . The apparatus of claim 1 , wherein the voltage applied by the one or more control circuits to the unselected drain side select lines of the unselected sub-blocks has a magnitude of approximately the second erase voltage pulse,
wherein a combination of the voltages applied to the unselected bit lines and the drain side select line of the selected sub-block does not create GIDL current in the first group of NAND strings, wherein a combination of the voltages applied to the selected bit lines and the unselected drain side select lines does not create GIDL current in the first plurality of the NAND strings in the third group of NAND strings, wherein a combination of the voltages applied to the unselected bit lines and the unselected drain side select lines does not create GIDL current in the second plurality of the NAND strings in the third group of NAND strings.
3 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
inhibit erase of unselected memory cells that are connected to unselected word lines in the selected block while applying the erase condition to the second group of the memory cells.
4 . The apparatus of claim 1 , wherein the erase conditions include a single application of the second erase voltage pulse to the selected bit lines.
5 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
float a source line connected to the NAND strings in the selected block while applying the erase conditions to the second group of the memory cells.
6 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
program the first group of the memory cells from the erase state to at least 15 target data states, the target data states associated with different target threshold voltages.
7 . The apparatus of claim 1 , wherein:
the drain side select line in each sub-block is a first drain side select line in a first drain side select layer of the conductive layers and is connected to a first drain side select transistor on each NAND string in the sub-block;
each sub-block further includes a second drain side select line in a second drain side select layer of the conductive layers and is connected to a second drain side select transistor on each NAND string in the sub-block; and
the one or more control circuits are further configured to apply substantially the same voltage to the second drain side select line in all sub-blocks in the selected block while applying the erase conditions to the second group of the memory cells in the selected sub-block while inhibiting erase of all other memory cells in the selected block.
8 . The apparatus of claim 1 , wherein:
the drain side select line in each sub-block is a first drain side select line in a first drain side select layer of the conductive layers and is connected to a first drain side select transistor on each NAND string in the sub-block;
each sub-block further includes a second drain side select line in a second drain side select layer of the conductive layers and is connected to a second drain side select transistor on each NAND string in the sub-block; and
the one or more control circuits are further configured to apply substantially the same voltage to the second drain side select line in the selected sub-block and to the unselected bit lines associated with the first group of NAND strings while applying the erase conditions to the second group of the memory cells in the selected sub-block while inhibiting erase of all other memory cells in the selected block.
9 . The apparatus of claim 8 , wherein the one or more control circuits are further configured to apply the substantially the same voltage to the second drain side select line in the unselected sub-blocks and to the unselected bit lines associated with the first group of NAND strings while applying the erase conditions to the second group of the memory cells in the selected sub-block while inhibiting erase of all other memory cells in the selected block.
10 . A method of operating three-dimensional NAND memory, the method comprising:
erasing a group of memory cells in a selected block in the three-dimensional NAND memory, to an erase state associated with an erase threshold voltage, wherein the selected block has word lines and NAND strings, each NAND string in the selected block having memory cells and a drain side select transistor, each word line connecting to one memory cell on each NAND string in the selected block, the selected block divided into sub-blocks with each sub-block having a group of the NAND strings, each sub-block having a drain side select line connected to the drain side select transistor on each NAND string in the sub-block, including applying a first erase voltage pulse to bit lines associated with the NAND strings in the selected block while applying a voltage to the drain side select lines of the selected block to create gate-induced drain leakage (GIDL) currents in the NAND strings of the selected block and while applying a non-negative erase enable voltage to the word lines of the selected block;
programming a first group of memory cells on a selected word line in a selected sub-block of the selected block from the erase state to target threshold voltages associated with corresponding data states, wherein the first group of memory cells reside on a first group of the NAND strings in the selected sub-block and are connected to a selected word line of the word lines in the selected block;
inhibiting programming of a second group of memory cells on the selected word line in the selected sub-block while programming the first group of memory cells, wherein the second group are connected to the selected word line, the second group of the memory cells reside on a second group of the NAND strings in the selected sub-block; and
applying erase conditions to the second group of the memory cells in the selected sub-block while inhibiting erase of all other memory cells in the selected block after programming the first group to lower threshold voltages of respective memory cells in the second group, including applying a second erase voltage pulse to selected bit lines associated with the second group of the NAND strings while applying a GIDL voltage to the drain side select line in the selected sub-block to create GIDL currents in the second group of the NAND strings and while applying the non-negative erase enable voltage to the selected word line, wherein inhibiting erase of all other memory cells in the selected block includes applying a voltage that is less than a magnitude of the second erase voltage pulse to unselected bit lines associated with the first group of NAND strings while applying a voltage greater than the GIDL voltage to unselected drain side select lines of unselected sub-blocks in the selected block, wherein a first plurality of the NAND strings in the unselected sub-blocks are associated with the selected bit lines and a second plurality of the NAND strings in the unselected sub-blocks are associated with the unselected bit lines.
11 . A non-volatile storage system, the system comprising:
a three-dimensional memory structure comprising blocks, each block having a stack of alternating dielectric layers and conductive layers and NAND strings extending through the alternating dielectric layers and conductive layers, each NAND string having memory cells and a drain side select transistor, the conductive layers including word lines with each word line connecting to one memory cell on each NAND string in the block, each block divided into sub-blocks with each sub-block having a group of the NAND strings, each sub-block having a drain side select line in a drain side select layer of the conductive layers, the drain side select line of the sub-block connecting to the drain side select transistor on each NAND string in the sub-block, the three-dimensional memory structure having bit lines associated with the NAND strings in the blocks;
first erase means for erasing memory cells in a selected block to an erase state, the erase state associated with an erase threshold voltage, the first erase means further for applying a first erase voltage pulse to the bit lines associated with the NAND strings of the selected block while applying a voltage to the drain side select lines of the selected block to create gate-induced drain leakage (GIDL) currents in the NAND strings of the selected block and while applying a non-negative erase enable voltage to the word lines of the selected block;
program means for programming a first group of the memory cells connected to a selected word line in a selected sub-block in the selected block from the erase state to target data states while inhibiting a second group of the memory cells connected to the selected word line in the selected sub-block from programming from the erase state and inhibiting a third group of memory cells on the selected word line in unselected sub-blocks in the selected block from programming, each target data state associated with a threshold voltage that is greater than the erase threshold voltage, the first group of the memory cells on a first group of the NAND strings in the selected sub-block, the second group of memory cells on a second group of the NAND strings in the selected sub-block, the third group of memory cells residing on a third group of NAND strings in the unselected sub-blocks; and
post-program erase means for applying erase conditions to the second group of the memory cells to lower the threshold voltage of respective memory cells in the second group while inhibiting erase of all other memory cells in the selected block after the first group of the memory cells are programmed to the target data states, wherein prior to applying the erase conditions the second group contains memory cells having a threshold voltage above an erase threshold voltage and memory cells having a threshold voltage below the erase threshold voltage, the post-program erase means for further for applying a second erase voltage pulse to selected bit lines associated with the second group of the NAND strings while applying a GIDL voltage to the drain side select line of the selected sub-block to create GIDL currents in the second group of the NAND strings and while applying the non-negative erase enable voltage to the selected word line, wherein inhibiting erase of all other memory cells in the selected block includes applying a voltage that is less than a magnitude of the second erase voltage pulse to unselected bit lines associated with the first group of NAND strings while applying a voltage greater than the GIDL voltage to unselected drain side select lines of the unselected sub-blocks, wherein a first plurality of the NAND strings in the unselected sub-blocks are associated with the selected bit lines and a second plurality of the NAND strings in the unselected sub-blocks are associated with the unselected bit lines.
12 . The non-volatile storage system of claim 11 , wherein the post-program erase means is further for:
applying the second erase voltage pulse to the selected bit lines associated with the second group of the NAND strings a single time without an erase verify.
13 . The non-volatile storage system of claim 11 , wherein the post-program erase means is further for:
floating a source line in the selected block while generating the GIDL currents in the second group of the NAND strings.
14 . The non-volatile storage system of claim 11 , wherein the voltage applied to the unselected drain side select lines of the unselected sub-blocks has a magnitude of approximately the second erase voltage.