IP Library Granted Patent US 12,260,085
Granted Patent B2
US 12,260,085 · App. 18/361,093 · Granted Mar 25, 2025

Dynamically determining a memory block threshold for initiating a garbage collection process

Inventors: Anamika Choudhary (Bangalore, IN); Disha Sharma (Bangalore, IN)
Assignee: Sandisk Technologies, Inc.
G06F3/0608G06F3/064G06F3/0652G06F3/0659G06F3/0679G06F12/0246
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Quick Facts
Patent No.
US 12,260,085
App. No.
18/361,093
Granted
Mar 25, 2025
Kind
B2
Abstract

A write pattern of a host device is used to dynamically determine when to initiate a garbage collection process on a data storage device. The write pattern of the host device is based on a number of I/O commands received from the host device and on a number of available memory blocks in the data storage device. If the write pattern of the host device indicates that fewer than a threshold number of memory blocks will be available after a predetermined number of additional I/O commands are received, the garbage collection process is initiated. An amount of valid data that is transferred from one memory location to another memory location during the garbage collection process is also dynamically determined. Thus, a garbage collection process may be tailored to a specific host device.

Claims (37)

1. A method, comprising:

tracking a number of commands received from a host device;

determining a number of free memory blocks in a data storage device based, at least in part, on a predetermined number of commands being received;

generating a data point based, at least in part, on the number of received commands and the determined number of free memory blocks;

determining a write pattern of the host device based, at least in part, on a determination that a plurality of data points have been generated; and

initiating a garbage collection process based, at least in part, on the determined write pattern of the host device.

2. The method of claim 1 , further comprising determining whether the determined write pattern of the host device will cause the number of free memory blocks to fall below a free memory block threshold after a predetermined number of additional commands are received.

3. The method of claim 2 , further comprising determining an average valid fragment count (VFC) of the data storage device based, at least in part, on determining that the write pattern of the host device will cause the number of free memory blocks to fall below the free memory block threshold.

4. The method of claim 3 , further comprising transferring an amount of data from a first memory location in the data storage device to a second memory location in the data storage device during the garbage collection process based, at least in part, on the average VFC.

5. The method of claim 3 , further comprising storing the average VFC in the data storage device.

6. The method of claim 1 , wherein the write pattern of the host device is determined using a linear regression model.

7. The method of claim 1 , further comprising storing the generated data point.

8. A data storage device, comprising:

a controller; and

one or more memory devices communicatively coupled to the controller and storing instructions that, when executed by the controller, cause the controller to:

track a number of commands received from a host device;

determine a number of free memory blocks in the data storage device, based, at least in part, on a predetermined number of commands being received;

store the number of commands received from the host device and the determined number of free memory blocks as a data point;

determine a write pattern of the host device based, at least in part, on a number of data points exceeding a data point threshold; and

initiate a garbage collection process based, at least in part, on the determined write pattern of the host device.

9. The data storage device of claim 8 , further comprising instructions for causing the controller to determine whether the determined write pattern of the host device will cause the number of free memory blocks to fall below a free memory block threshold after a predetermined number of additional commands are received.

10. The data storage device of claim 9 , further comprising instructions for causing the controller to determine an average valid fragment count (VFC) of the data storage device based, at least in part, on determining the write pattern of the host device will cause the number of free memory blocks to fall below the free memory block threshold.

11. The data storage device of claim 10 , further comprising instructions for transferring an amount of data from a first memory location in the data storage device to a second memory location in the data storage device during the garbage collection process based, at least in part, on the average VFC.

12. The data storage device of claim 10 , further comprising instructions for causing the controller to store the average VFC.

13. The data storage device of claim 8 , wherein the write pattern of the host device is determined using a linear regression model.

14. The data storage device of claim 13 , wherein the data points are used to determine a regression line using the linear regression model.

15. A data storage device, comprising:

means for tracking a number of commands received from a host device;

means for determining a number of free memory blocks in the data storage device, based, at least in part, on a predetermined number of commands being received;

means for generating a plurality of data points based, at least in part, on the number of commands received from the host device and the number of free memory blocks in the data storage device;

means for determining a write pattern of the host device based, at least in part, on the generated plurality of data points; and

means for initiating a garbage collection process based, at least in part, on the determined write pattern of the host device.

16. The data storge device of claim 15 , further comprising means for determining whether the determined write pattern of the host device will cause the number of free memory blocks to fall below a free memory block threshold after a predetermined number of additional commands are received.

17. The data storage device of claim 16 , further comprising means for determining an average valid fragment count (VFC) of the data storage device.

18. The data storage device of claim 17 , wherein the garbage collection process transfers a first amount of data from a first memory location in the data storage device to a second memory location in the data storage device based, at least in part, on the average VFC having a first value and wherein the garbage collection process transfers a second amount of data from the first memory location in the data storage device to the second memory location in the data storage device based, at least in part, on the average VFC having a second value.

19. The data storage device of claim 15 , wherein the write pattern of the host device is determined using a linear regression model.

20. The data storage device of claim 19 , further comprising means for determining a regression line, the regression line being based, at least in part, on the generated plurality of data points and the linear regression model.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2023
From: CHOUDHARY, ANAMIKA; SHARMA, DISHA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064422/0667 →
Continuity (2)
Provisional Application 63508799 · Jun 16, 2023
Related Publication 20240419326A1 · Dec 19, 2024
References Cited (7)
US 11556258B1 · Huang · 2023 [cited by examiner]
US 11599298B1 · B N · 2023 [cited by examiner]
US 11768617B2 · Kim · 2023 [cited by examiner]
US 20120159051A1 · Hida · 2012 [cited by examiner]
US 20140181370A1 · Cohen · 2014 [cited by examiner]
US 20200104254A1 · Lee · 2020 [cited by examiner]
US 20220398029A1 · A · 2022 [cited by examiner]
Cited By (1)
US 12,449,996