IP Library Granted Patent US 12,475,958
Granted Patent B2
US 12,475,958 · App. 18/361,841 · Granted Nov 18, 2025

Non-volatile memory with decline state operation

Inventors: Liang Li (Shanghai, CN); Ming Wang (Shanghai, CN); Jiahui Yuan (Fremont, CA)
Assignee: Sandisk Technologies, Inc.
G11C16/3459G11C16/102G11C16/14
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,475,958
App. No.
18/361,841
Granted
Nov 18, 2025
Kind
B2
Abstract

A non-volatile memory is configured to transition memory cells from programmed data states with the higher ranges of threshold voltages to programmed data states with the lower ranges of threshold voltages without the transitioning the memory cells to the erased data state.

Claims (51)

1 . A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells, each of the memory cells is configured to store data in a set of data states, each of the data states correspond to a range of threshold voltages, the set of data states include an erased data state and multiple programmed data states; and

a control circuit connected to the memory cells, the control circuit is configured to:

receive first data and store the first data into the non-volatile memory cells by programming the non-volatile memory cells to the multiple programmed data states;

receive new data to be programmed into the non-volatile memory cells already storing the first data in the multiple programmed data states;

compare the new data to the first data to identify a subset of memory cells in the multiple programmed data states with higher threshold voltages that need to transition to programmed data states with lower ranges of threshold voltages in order to store the new data; and

transitioning the identified memory cells from the multiple programmed data states with higher threshold voltages to programmed data states with lower ranges of threshold voltages without the transitioning the identified memory cells to the erased data state.

2 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to transition the first memory cell from the the multiple programmed data states with higher threshold voltages to programmed data states with lower ranges of threshold voltages by using gate induced drain leakage (GIDL) to lower threshold voltage of the first memory cell.

3 . The non-volatile storage apparatus of claim 1 , wherein:

the multiple programmed data states comprise a first data state adjacent the erased data state and a highest data state furthest from the erased data state in terms of threshold voltage, the highest data state has a highest range of threshold voltages of the set of data states, the multiple programmed data states correspond to higher threshold voltages than the erased data state.

4 . The non-volatile storage apparatus of claim 3 , wherein:

the control circuit is configured to program memory cells in the direction from the erased data state toward the highest data state and erase memory cells in the direction from the highest data state toward the erased data state.

5 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to persistently maintain the identified memory cells in the programmed data states with lower ranges of threshold voltages after the transition.

6 . The non-volatile storage apparatus of claim 5 , wherein:

the control circuit is configured to perform other memory operations after the transition.

7 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to verify that the identified memory cells are in the programmed data states with lower ranges of threshold voltages-after the transition.

8 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to adjust the speed of the transition.

9 . The non-volatile storage apparatus of claim 1 , further comprising:

a bit line connected to the first memory cell, the control circuit is configured to:

apply a bit line voltage to the bit line to cause the transition, and

adjust the bit line voltage in order to adjust the speed of the transition.

10 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to adjust speed of the transition based on rate of change of threshold voltage of the identified memory cells.

11 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to adjust speed of the transition during the transition.

12 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to sense threshold voltage of the identified memory cells part way through the transition and, subsequently, adjust speed of the transition based on the sensed threshold voltage.

13 . A method of programming non-volatile memory cells, each of the memory cells are configured to store data in a set of data states, each of the data states correspond to a range of threshold voltages, the set of data states include an erased data state and multiple programmed data states, the method comprising:

receiving first data and storing the first data into a set of the non-volatile memory cells by programming the set of the non-volatile memory cells to the multiple programmed data states;

receiving new data to be programmed into the set of non-volatile memory cells already storing the first data in the multiple programmed data states;

comparing the new data to the first data to identify a subset of memory cells in the multiple programmed data states with higher threshold voltages that need to transition to programmed data states with lower ranges of threshold voltages in order to store the new data; and

transitioning the identified memory cells from the multiple programmed data states with higher threshold voltages to programmed data states with lower ranges of threshold voltages without the transitioning the identified memory cells to the erased data state.

14 . The method of claim 13 , further comprising:

performing other memory operations after the transitioning; and

the control circuit is configured to persistently maintain the identified memory cells in the programmed data states with the lower threshold voltages during and after the other memory operations.

15 . The method of claim 14 , wherein:

the transitioning comprises verifying that the identified memory cells are in the programmed data states with the lower threshold voltages.

16 . The method of claim 13 , further comprising:

sensing threshold voltages of the identified memory cells; and

adjusting speed of the transitioning based on the sensing.

17 . A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells, each of the memory cells are configured to separately store data in a set of data states, each of the data states correspond to a range of threshold voltages, the set of data states include an erased data state and multiple programmed data states, the multiple programmed data states comprise a first data state adjacent to the erased data state and a highest data state furthest from the erased data state in terms of threshold voltage, the highest data state has a highest range of threshold voltages of the set of data states; and

means for:

receiving first data and storing the first data into the non-volatile memory cells by programming the non-volatile memory cells to the multiple programmed data states;

receiving new data to be programmed into the non-volatile memory cells already storing the first data in the multiple programmed data states;

comparing the new data to the first data to identify a subset of memory cells in the multiple programmed data states with higher threshold voltages that need to transition to programmed data states with lower ranges of threshold voltages in order to store the new data; and

transitioning the identified memory cells from the multiple programmed data states with higher threshold voltages to programmed data states with lower ranges of threshold voltages without the transitioning the identified memory cells to the erased data state.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2023
From: LI, LIANG; WANG, MING; YUAN, JIAHUI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064572/0867 →
Continuity (2)
Provisional Application 63505306 · May 31, 2023
Related Publication 20240404608A1 · Dec 5, 2024
References Cited (15)
US 7495954B2 · Ito · 2009 [cited by applicant]
US 7965554B2 · Lutze et al. · 2011 [cited by applicant]
US 9449698B1 · Paudel et al. · 2016 [cited by applicant]
US 9552885B2 · Shukla et al. · 2017 [cited by applicant]
US 9711229B1 · Rabkin et al. · 2017 [cited by applicant]
US 20130265830A1 · Bisen · 2013 [cited by applicant]
US 20130279256A1 · Costa · 2013 [cited by examiner]
US 20140029343A1 · Yasuda · 2014 [cited by examiner]
US 20150016186A1 · Shen · 2015 [cited by applicant]
US 20200152271A1 · Sakui et al. · 2020 [cited by applicant]
US 20230154551A1 · Ko · 2023 [cited by examiner]
JP 2010097676A · 2010 [cited by applicant]
JP 2023512246A · 2023 [cited by applicant]
WO 2022186846A1 · 2022 [cited by applicant]
Liu, Chun-Yi, et al. “PEN: Design and Evaluation of Partial-Erase for 3D NAND-Based High Density SSDs”, 16th USENIX Conference on File and Storage Technogies, Feb. 12-15, 2018, pp. 70-82. [cited by applicant]