Non-target on-die termination
Technology for a memory system having on-die termination (ODT) in a non-target memory die. A read enable path of a first die and a data strobe path of a second die are connected to a first electrical line. However, a data strobe path of the second die and a read enable path of the first die are connected to a second electrical line. Each die contains detection circuit that detects a condition of line that carries a read enable signal when that die is a non-target. The die enables ODT to provide termination resistance for the electrical line that carries the read enable signal when that die is the non-target.
1 . An apparatus, comprising:
a communication link having a first channel and a second channel;
a first memory die connected to the communication link, wherein the first memory die is configured to send a first data strobe signal over the first channel and receive a first read enable signal on the second channel when the first memory die is a target die for a first read command; and
a second memory die connected to the communication link, the second memory die having on-die termination (ODT) configured to provide termination resistance to the second channel, wherein the second memory die is configured to send a second data strobe signal over the second channel and receive a second read enable signal on the first channel when the second memory die is a target of a second read command, wherein the second memory die is configured to enable the second ODT responsive to a condition of the first read enable signal on the second channel when the first memory die is a target of the first read command and the second memory die is a non-target of the first read command.
2 . The apparatus of claim 1 , wherein the condition of the first read enable signal is a transition of the first read enable signal on the second channel during an initial phase of the first read command.
3 . The apparatus of claim 2 , wherein:
the first read enable signal is active low, the second memory die is configured to detect the first read enable signal transition from high to low as the condition to enable the second ODT.
4 . The apparatus of claim 2 , wherein:
the first read enable signal is active high, the second memory die is configured to detect the first read enable signal transition from low to high as the condition to enable the second ODT.
5 . The apparatus of claim 2 , wherein:
the first memory die includes first on-die termination (ODT) configured to provide termination resistance to the first channel, the ODT of the second memory die is second ODT; and
the first memory die is configured to enable the first ODT responsive to detection of a transition of the second read enable signal on the first channel during an initial phase of the second read command when the second memory die is a target of the second read command and the first memory die is a non-target of the second read command.
6 . The apparatus of claim 5 , wherein:
the first memory die further includes a first edge detection circuit coupled to the first channel, the first edge detection circuit configured to detect an edge of the second read enable signal on the first channel during an initial phase of the second read command when the first memory die is a non-target of the second read command; and
the second memory die further includes a second edge detection circuit coupled to the second channel, the second edge detection circuit configured to detect an edge of the first read enable signal on the second channel during an initial phase of the first read command when the second memory die is a non-target of the first read command.
7 . The apparatus of claim 6 , wherein:
the first edge detection circuit comprises a first latch configured to detect an edge of the second read enable signal on the first channel; and
the second edge detection circuit comprises a second latch configured to detect an edge of the first read enable signal on the second channel.
8 . The apparatus of claim 6 , wherein:
the first channel comprises a first differential channel having a first electrical line and a second electrical line, the first edge detection circuit has a first input coupled to the first electrical line of the first channel to sample the second read enable signal when the first memory die is the non-target of the second read command; and
the second channel comprises a second differential channel having a third electrical line and a fourth electrical line, the second edge detection circuit has a first input coupled to the third electrical line of the second channel to sample the first read enable signal when the second memory die is the non-target of the first read command.
9 . The apparatus of claim 1 , wherein the second memory die is configured to disable the second ODT responsive to a condition of a read enable signal on the second channel when the first memory die is a target of a write command and the second memory die is a non-target of the write command.
10 . The apparatus of claim 1 , further comprising:
a memory controller communicatively coupled with the first memory die and the second memory die by the communication link, wherein the memory controller is configured to:
select the first memory die as the target for the first read command while not selecting the second memory die for the first read command;
provide the first read enable signal on the second channel while the first memory die is the target of the first read command; and
receive the first data strobe signal on the first channel while the first memory die is the target of the first read command.
11 . A method for operating a memory system, the method comprising:
determining, by a first memory die, that the first memory die is a target of a first read command from a memory controller;
receiving a first read enable signal over a first electrical line connected to a first pad on the first memory die, the first read enable signal being a first control signal from the memory controller to instruct the first memory die to transmit data for the first read command;
transferring a data strobe signal from the first memory die over a second electrical line connected to a second pad on the first memory die, the data strobe signal being a second control signal for data transferred from the first memory die over a data input/output (I/O) channel between the first memory die and the memory controller in response to the first read command;
determining, by the first memory die, that the first memory die is a non-target of a second read command from the memory controller;
sampling the second electrical line for a second read enable signal during an initial phase of the second read command, the second read enable signal being a third control signal from the memory controller to instruct a second memory die to transmit data for the second read command; and
activating on-die termination (ODT) connected to the second pad to provide termination resistance on the first memory die to the second electrical line responsive to detecting a transition of the second read enable signal to an active state during the initial phase of the second read command.
12 . The method of claim 11 , wherein detecting the transition of the second read enable signal comprises:
detecting a transition of the second read enable signal from a high state to a low state during the initial phase of the second read command.
13 . The method of claim 11 , wherein detecting the transition of the second read enable signal comprises:
detecting a transition of the second read enable signal from a low state to a high state during the initial phase of the second read command.
14 . The method of claim 11 , further comprising:
determining, by the first memory die, that the first memory die is a non-target of a write command;
sampling the second electrical line for a third read enable signal during an initial phase of the write command; and
de-activating the on-die termination (ODT) connected to the second pad responsive to detecting no transition of the third read enable signal during the initial phase of the write command.
15 . A memory system comprising:
a communication link having a first electrical line and a second electrical line;
a first memory die communicatively coupled with the communication link, the first memory die having a first data strobe pad connected to the first electrical line and a first read enable pad connected to the second electrical line, the first memory die having first on-die termination (ODT) configured to provide termination resistance at an end the first electrical line that connects to the first data strobe pad; and
a second memory die communicatively coupled with the communication link, the second memory die having a second data strobe pad connected to the second electrical line and a second read enable pad connected to the first electrical line, the second memory die having second on-die termination (ODT) configured to provide termination resistance at an end the second electrical line that connects to the second data strobe pad;
wherein the first memory die is configured to enable the first ODT responsive to detection of a transition of a first read enable signal on the first electrical line during an initial phase of a first read command when the second memory die is a target of the first read command and the first memory die is a non-target of the first read command; and
wherein the second memory die is configured to enable the second ODT responsive to detection of a transition of a second read enable signal on the second electrical line during an initial phase of a second read command when the first memory die is a target of the second read command and the second memory die is a non-target of the second read command.
16 . The memory system of claim 15 , wherein:
the first memory die further includes a first edge detection circuit coupled to the first electrical line, the first edge detection circuit configured to detect a falling edge of the second read enable signal on the first electrical line when the first memory die is the non-target of the second read command; and
the second memory die further includes a second edge detection circuit coupled to the second electrical line, the second edge detection circuit configured to detect a falling edge of the first read enable signal on second first electrical line when the second memory die is the non-target of the first read command.
17 . The memory system of claim 15 , wherein:
the first memory die further includes a first edge detection circuit coupled to the first electrical line, the first edge detection circuit configured to detect a rising edge of the second read enable signal on the first electrical line when the first memory die is the non-target of the second read command; and
the second memory die further includes a second edge detection circuit coupled to the second electrical line, the second edge detection circuit configured to detect a rising edge of the first read enable signal on second first electrical line when the second memory die is the non-target of the first read command.
18 . The memory system of claim 15 , further comprising a memory controller communicatively coupled with the first memory die and the second memory die by the communication link, wherein the memory controller is configured to:
select the second memory die as the target for the first read command while not selecting the first memory die for the first read command; and
provide the first read enable signal on the first electrical line while the second memory die is the target of the first read command.
19 . The memory system of claim 18 , wherein:
the second memory die is further configured to send a data strobe signal to the memory controller on the second electrical line responsive to transitions of the first read enable signal on the first electrical line during the first read command.
20 . The memory system of claim 15 , wherein:
the first memory die is configured to disable the first ODT responsive to no transition of a third read enable signal on the first electrical line during an initial phase of a first write command when the second memory die is a target of the first write command and the first memory die is a non-target of the first write command; and
the second memory die is configured to disable the second ODT responsive to no transition of a fourth read enable signal on the second electrical line during an initial phase of a second write command when the first memory die is a target of the second write command and the second memory die is a non-target of the second write command.