Apparatus and methods for read retry with conditional data refresh

1 . An apparatus comprising:

a memory structure comprising non-volatile memory cells;

a control circuit coupled to the memory structure, the control circuit configured to:

first read a block of non-volatile memory cells using a first plurality of read levels;

determine that the first read fails to successfully read the block of non-volatile memory cells;

second read the block of memory cells using a second plurality of read levels different from the first plurality of read levels;

determine that the second read successfully reads the block of non-volatile memory cells;

estimate that the first read failed because of data retention or read disturb; and

erase and re-write data to the block of non-volatile memory cells.

2 . The apparatus of claim 1 , wherein the first read levels comprise default read levels.

3 . The apparatus of claim 1 , wherein the second read levels comprise re-tuned read levels.

4 . The apparatus of claim 1 , wherein:

the first plurality of read levels comprises a first read level and a second read level;

the second plurality of read levels comprises a third read level and a fourth read level; and

the control circuit is configured to estimate that the first read failed because the block of memory cells comprises data retention or read disturb greater than a predetermined amount by:

determining that a first difference between the first read level and the third read level is greater than a first threshold or determining that a second difference between the second read level and the fourth read level is greater than a second threshold.

5 . The apparatus of claim 4 , wherein:

the first read level and third read level each comprise a highest read level; and

the second read level and the fourth read level each comprise a lowest read level.

6 . The apparatus of claim 4 , wherein:

the block of non-volatile memory cells comprises a plurality of programmed states;

the first read level and the third second level each correspond to a first one of the programmed states; and

the second read and the fourth read level each correspond to a second one of the programmed states.

7 . The apparatus of claim 4 , wherein:

the block of non-volatile memory cells comprises a highest programmed state and a lowest programmed state;

the first read level and the third second level each correspond to the highest programmed state; and

the second read and the fourth read level each correspond to the lowest programmed state.

8 . The apparatus of claim 1 , wherein the control circuit is further configured to immediately erase and re-write data to the block of non-volatile memory cells.

9 . The apparatus of claim 1 , wherein the control circuit is further configured to flag the block of non-volatile memory cells and erase and re-write data to the block of non-volatile memory cells as a background operation.

10 . The apparatus of claim 1 , wherein the memory structure comprises a three dimensional array of non-volatile memory cells.

11 . The apparatus of claim 1 , wherein the non-volatile memory cells comprise NAND strings.

12 . A method comprising:

first reading a block of non-volatile memory cells using default read levels;

determining that the first read failed to successfully read the block of non-volatile memory cells;

re-tuning the first read levels to determine re-tuned read levels each associated with a corresponding default read level;

second reading the block of non-volatile memory cells using the re-tuned read levels;

determining a first difference between a first default read level and a corresponding first re-tuned read level;

predicting based on the first difference that the first read failed because of data retention or read disturb; and

re-writing data to the block of non-volatile memory cells.

13 . The method of claim 12 , further comprising re-writing data to the block of non-volatile memory cells without first erasing the block of non-volatile memory cells.

14 . The method of claim 12 , wherein the first default read level is associated with a highest programmed state of the block of non-volatile memory cells.

15 . The method of claim 12 , further comprising:

determining a second difference between a second default read level and a corresponding second re-tuned read level; and

predicting that the first read failed based on the first difference or the second difference.

16 . The method of claim 15 , wherein the second default read level is associated with a lowest programmed state of the block of non-volatile memory cells.

17 . The method of claim 15 , further comprising erasing the block of memory cells prior to re-writing data to the block of non-volatile memory cells.

18 . The method of claim 12 , further comprising immediately re-writing data to the block of non-volatile memory cells.

19 . The method of claim 12 , further comprising flagging the block of non-volatile memory cells and re-writing data to the block of non-volatile memory cells as a background operation.

20 . Apparatus comprising:

a plurality of non-volatile memory cells;

a control circuit coupled to the non-volatile memory cells, the control circuit configured to:

first read a block of non-volatile memory cells using a first setoff read parameters;

determine that the first read fails to successfully read the block of non-volatile memory cells;

second read the block of memory cells using a second set of read parameters different from the first plurality of read levels;

determine that the second read successfully reads the block of non-volatile memory cells;

predict that the first read failed because of read disturb; and

re-write data to the block of non-volatile memory cells.