IP Library › Assignment 008811/0577
Patent Assignment
Reel/Frame 008811/0577

Merger

Recorded: 1997-11-12 Pages: 13
Assignor
Assignee
ALTERA CORPORATION (A CORPORATION OF DELAWARE)
101 INNOVATION DRIVE, SAN JOSE, CALIFORNIA, 95134
Covered Properties (70)
Programmable Integrated Circuit Logic Array Device Having Improved Microprocessor Connectability
Patent: 4,969,121 →
Application: 07/020,556 →
Multifunction Flip-Flop-Type Circuit
Patent: 4,864,161 →
Application: 07/190,530 →
Programmable Logic Device with Programmable Word Line Connections
Patent: 4,903,223 →
Application: 07/190,571 →
Programmable Logic Device with Array Blocks Connected via Programmable Interconnect
Patent: 4,871,930 →
Application: 07/190,663 →
Bit Line Sense Amplifier for Programmable Logic Devices
Patent: 4,899,070 →
Application: 07/218,556 →
Programmable Interface for Computer System Peripheral Circuit Card
Patent: 5,111,423 →
Application: 07/222,565 →
Programmable Logic Devices with Spare Circuits for Use in Replacing Defective Circuits
Patent: 4,899,067 →
Application: 07/222,832 →
Method and Apparatus for Programming and Verifying Programmable Elements in Programmable Devices
Patent: 4,930,107 →
Application: 07/229,852 →
Programmable Logic Device with Array Blocks with Programmable Clocking
Patent: 4,912,342 →
Application: 07/407,411 →
Integrated Circuits with Reduced Switching Noise
Patent: 5,066,873 →
Application: 07/444,993 →
Methods and Apparatus for Reducing Coupling Noise in Programmable Logic Devices
Patent: 5,091,661 →
Application: 07/587,075 →
Reference Voltage Generator
Patent: 5,045,772 →
Application: 07/591,363 →
Sense Amplifier with Increased Speed and Reduced Power Consumption
Patent: 5,128,565 →
Application: 07/596,764 →
Methods and Apparatus for Facilitatiang Scan Testing of Asynchronous Logic Circuitry
Patent: 5,166,604 →
Application: 07/611,974 →
Apparatus and Method for Measuring Gate Delays in Integrated Circuit Wafers
Patent: 5,097,208 →
Application: 07/622,615 →
Registered Logic Macrocell with Product Term Allocation and Adjacent Product Term Stealing
Patent: 5,121,006 →
Application: 07/688,252 →
High-Density Erasable Programmable Logic Device Architecture Using Multiplexer Interconnections
Patent: 5,241,224 →
Application: 07/691,640 →
Complementary Low Power Non-Volatile Reconfigurable Eecell
Patent: 5,272,368 →
Application: 07/698,084 →
Zero Power, High Impedance Ttl-to-Cmos Converter
Patent: 5,144,167 →
Application: 07/701,686 →
Methods for Allocating Circuit Elements Between Circuit Groups
Patent: 5,341,308 →
Application: 07/702,001 →
Method of Programming Floating Gate Memory Devices Aided by Potential Applied to Read Channel
Patent: 5,247,477 →
Application: 07/708,241 →
Programmable Logic Element Interconnections for Programmable Logic Array Integrated Circuits
Patent: 5,260,610 →
Application: 07/754,017 →
Method for Programming Programmable Elements in Programmable Devices
Patent: 5,200,920 →
Application: 07/759,944 →
Method and Apparatus for Erasing an Array of Electrically Erasable Eprom Cells
Patent: 5,138,576 →
Application: 07/788,606 →
Method and Apparatus for Preventing Overerasure in a Flash Cell
Patent: 5,220,533 →
Application: 07/788,607 →
Sense Amplifier for Programmable Logic Device
Patent: 5,162,680 →
Application: 07/808,593 →
Programmable Transfer-Devices
Patent: 5,247,478 →
Application: 07/846,915 →
Eeprom-Backed Fifo Memory
Patent: 5,353,248 →
Application: 07/868,174 →
Registered Logic Macrocell with Product Term Allocation and Adjacent Product Term Stealing
Patent: 5,220,214 →
Application: 07/879,908 →
Look Up Table Implementation of Fast Carry for Adders and Counters
Patent: 5,274,581 →
Application: 07/880,752 →
Programmable Logic Array Integrated Circuits with Cascade Connections Between Logic Modules
Patent: 5,258,668 →
Application: 07/880,888 →
Methods and Apparatus for Programming Cellular Programmable Logic Integrated Circuits
Patent: 5,237,219 →
Application: 07/880,908 →
Programmable Logic Array Having Local and Long Distance Conductors
Patent: 5,260,611 →
Application: 07/880,942 →
Apparatus for Faciliting Scan Testing of Asynchronous Logic Circuitry
Patent: 5,285,153 →
Application: 07/947,729 →
Programmable Logic Devices with Spare Circuits for Replacement of Defects
Patent: 5,434,514 →
Application: 07/979,003 →
Programmable Logic Device Having Multiplexers and Demultiplexers Randomly Connected to Global Conductors for Interconnections Between Logic Elements
Patent: 5,371,422 →
Application: 08/038,787 →
Macrocell with Flexible Product Term Allocation
Patent: 5,350,954 →
Application: 08/039,927 →
Programmable Logic Device with Multiplexer-Based Programmable Interconnections
Patent: 5,376,844 →
Application: 08/039,944 →
High-Density Erasable Programmable Logic Device Architecture Using Multiplexer Interconnections
Patent: 5,268,598 →
Application: 08/043,146 →
High-Density Erasable Programmable Logic Device Architecture Using Multiplexer Interconnections
Patent: 5,384,499 →
Application: 08/123,435 →
Multiplexer Structures for Use in Making Controllable Interconnections in Integrated Circuits
Patent: 5,486,775 →
Application: 08/156,260 →
Eprom-Based Crossbar Switch with Zero Standby Power
Patent: 5,517,186 →
Application: 08/159,189 →
Look Up Table Implementaion of Fast Carry Arithmetic and Exclusive-or Operations
Patent: 5,481,486 →
Application: 08/166,300 →
Programmable Logic Device with Redundant Circuitry
Patent: 5,369,314 →
Application: 08/199,620 →
Programmable Logic Device with Logic Block Outputs Coupled to Adjacent Logic Block Output Multiplexers
Patent: 5,483,178 →
Application: 08/207,012 →
High-Density Erasable Programmable Logic Device Architecture Using Multiplexer Interconnections
Patent: 5,557,217 →
Application: 08/331,964 →
Programmable Logic Array with Local and Global Conductors
Patent: 5,485,103 →
Application: 08/356,516 →
Sense Amplifier with Feedback and Stabilization
Patent: 5,525,917 →
Application: 08/358,210 →
Programmable Logic Array Device with Grouped Logic Regions and Three Types of Conductors
Patent: 5,537,057 →
Application: 08/388,300 →
Programmable Logic Devices with Spare Circuits for Replacement of Defects
Patent: 5,485,102 →
Application: 08/416,296 →
Programmable Logic Array Integrated Circuit Devices
Patent: 5,689,195 →
Application: 08/442,795 →
Programmable Logic Array Integrated Circuits with Interconnection Conductors of Overlapping Extent
Patent: 5,592,106 →
Application: 08/442,796 →
Techniques for Programming Programmable Logic Array Devices
Patent: 5,543,730 →
Application: 08/442,801 →
Programmable Logic Array Integrated Circuits with Blocks of Logic Regions Grouped into Super-Blocks
Patent: 5,541,530 →
Application: 08/442,802 →
Programmable Logic Array Devices with Interconnect Lines of Various Lengths
Patent: 5,543,732 →
Application: 08/442,832 →
Programmable Logic Array Integrated Circuits with Segmented, Selectively Connectable, Long Interconnection Conductors
Patent: 5,614,840 →
Application: 08/443,119 →
Methods for Partitioning Circuits in Order to Allocate Elements Among Multiple Circuit Groups
Patent: 5,659,717 →
Application: 08/508,401 →
Programmable Logic Array Integrated Circuit Devices with Regions of Enhanced Interconnectivity
Patent: 5,565,793 →
Application: 08/517,596 →
Method of Fabricating Self-Aligned Planarized Well Structures
Patent: 5,523,247 →
Application: 08/518,802 →
Programmable Logic Array Integrated Circuit Devices with Flexible Carry Chains
Patent: 5,631,576 →
Application: 08/522,554 →
Routing Connections for Programmable Logic Array Integrated Circuits
Patent: 5,670,895 →
Application: 08/545,084 →
Means and Apparatus to Minimize the Effects of Silicon Processing Defects in Programmable Logic Devices
Patent: 5,592,102 →
Application: 08/545,437 →
Random Access Memory Block Circuitry for Programmable Logic Array Integrated Circuit Devices
Patent: 5,633,830 →
Application: 08/555,106 →
Apparatus for Serial Reading and Writing of Random Access Memory Arrays
Patent: 5,555,214 →
Application: 08/555,110 →
Programming Programmable Transistor Devices Using State Machines
Patent: 5,650,734 →
Application: 08/570,117 →
Programmable Logic Array Integrated Circuits with Carry and/or Cascade Rings
Patent: 5,672,985 →
Application: 08/574,351 →
High-Density Erasable Programmable Logic Device Architecture Using Multiplexer Interconnections, and Registered Macrocell with Product Term Allocation and Adjacent Product Term Stealing
Patent: 5,598,108 →
Application: 08/605,445 →
Programmable Logic Array Device with Grouped Logic Regions and Three Types of Conductors
Patent: 5,598,109 →
Application: 08/626,513 →
Loop Filter Level Detection Circuit and Method
Patent: 5,642,082 →
Application: 08/668,265 →
Technioues for Programming Programmable Logic Array Devices
Patent: 5,680,061 →
Application: 08/747,194 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. May 5, 1988
From: WONG, SAU-CHING; SO, HOCK-CHUEN; KOPEC, STANLEY J. JR.; HARTMANN, ROBERT F.
To: ALTERA CORPORATION, A CORP. OF CA
Reel/Frame 004881/0919 →
Assignment of Assignors Interest. May 5, 1988
From: NORMAN, KEVIN A.; SO, HOCK-CHUEN; VEENSTRA, KERRY S.; WONG, SAU-CHING
To: ALTERA CORPORATION
Reel/Frame 004893/0587 →
Assignment of Assignors Interest. May 5, 1988
From: NORMAN, KEVIN A.; FRANKOVICH, ROBERT J.
To: ALTERA CORPORATION
Reel/Frame 004899/0450 →
Assignment of Assignors Interest. Jul 13, 1988
From: OU, JUNG-HSING; WONG, SAU-CHING
To: ALTERA CORPORATION
Reel/Frame 004910/0678 →
Assignment of Assignors Interest. Jul 21, 1988
From: KOPEC, STANLEY J. JR.; CHAN, YIU-FAI; HARTMANN, ROBERT F.
To: ALTERA CORPORATION, 3525 MONROE STREET, SANTA CLARA, CA. 95051, A CORP. OF CA.
Reel/Frame 004914/0978 →
Assignment of Assignors Interest. Jul 22, 1988
From: SO, HOCK-CHUEN; WONG, SAU-CHING
To: ALTERA CORPORATION, 3525 MONROE STREET, SANTA CLARA, CALIFORNIA 95051 A CORP. OF CA
Reel/Frame 004926/0847 →
Assignment of Assignors Interest. Aug 8, 1988
From: CHAN, YIU-FAI; HUNG, CHUAN-YUNG
To: ALTERA CORPORATION, 3525 MONOROE STREET, SANTA CLARA, CALIFORNIA 95051, A CORP. OF CA
Reel/Frame 004916/0904 →
Assignment of Assignors Interest. Oct 30, 1989
From: WONG, SAU-CHING; SO, HOCK-CHUEN; KOPEC, STANLEY J. JR.; HARTMANN, ROBERT F.
To: ALTERA CORPORATION
Reel/Frame 005173/0117 →
Assignment of Assignors Interest. Dec 4, 1989
From: CHAN, YIU-FAI; HSIAO, CHANG-CHIA; WATSON, JAMES A.
To: ALTERA CORPORATION, 3525 MONROE STREET, SANTA CLARA, CA 95051 A CORP. OF CA
Reel/Frame 005188/0316 →
Assignment of Assignors Interest. Sep 24, 1990
From: CHIANG, DAVID
To: ALTERA CORPORATION
Reel/Frame 005460/0693 →
Assignment of Assignors Interest. Oct 1, 1990
From: NISHIWAKI, KUNIO; NORMAN, KEVIN A.
To: ALTERA CORPORATION
Reel/Frame 005470/0159 →
Assignment of Assignors Interest. Nov 13, 1990
From: AHANIN, BAHRAM; LYTLE, CRAIG S.; HO, RICKY W.
To: ALTERA CORPORATION
Reel/Frame 005507/0905 →
Assignment of Assignors Interest. Dec 5, 1990
From: CHIANG, DAVID
To: ALTERA CORPORATION
Reel/Frame 005532/0498 →
Assignment of Assignors Interest. Jan 7, 1991
From: MC CLINTOCK, CAMERON; SO, HOCK C.
To: ALTERA CORPORATION, A CORP. OF CA
Reel/Frame 005557/0309 →
Assignment of Assignors Interest. Apr 22, 1991
From: PEDERSEN, BRUCE B.
To: ALTERA CORPORATION
Reel/Frame 005692/0245 →
Assignment of Assignors Interest. May 10, 1991
From: TURNER, JOHN E.; CLIFF, RICHARD G.
To: ALTERA CORPORATION
Reel/Frame 005705/0707 →
Assignment of Assignors Interest. May 10, 1991
From: MCCLINTOCK, CAMERON
To: ALTERA CORPORATION
Reel/Frame 005857/0513 →
Assignment of Assignors Interest. May 31, 1991
From: NORMAN, KEVIN A.
To: ALTERA CORPORATION A CORP. OF CA
Reel/Frame 005731/0858 →
Assignment of Assignors Interest. Jul 1, 1991
From: PEDERSEN, BRUCE B.; CHIANG, DAVID; HEILE, FRANCIS B.; MCCLINTOCK, CAMERON
To: ALTERA CORPORATION, A CORPORATION OF CA
Reel/Frame 005755/0785 →
Assignment of Assignors Interest. Jul 5, 1991
From: MENDEL, DAVID W.
To: ALTERA CORPORATION, A CORP. OF CA.
Reel/Frame 005755/0364 →
Assignment of Assignors Interest. Sep 3, 1991
From: PEDERSEN, BRUCE B.; CLIFF, RICHARD G.; AHANIN, BAHRAM; LYTLE, CRAIG S.
To: ALTERA CORPORATION, A CORP. OF CA
Reel/Frame 005846/0241 →
Assignment of Assignors Interest. Nov 6, 1991
From: TURNER, JOHN E.
To: ALTERA CORPORATION, A CA CORP.
Reel/Frame 005910/0433 →
Assignment of Assignors Interest. Nov 6, 1991
From: MADURAWE, RAMINDA
To: ALTERA CORPORATION
Reel/Frame 005910/0310 →
Merger Mar 5, 1998
From: ALTERA CORPORATION, A CALIFORNIA CORPORATION
To: ALTERA CORPORATION, A DELAWARE CORPORATION
Reel/Frame 009015/0336 →
Security Interest Dec 17, 1999
From: SIVYER STELL CORPORATION
To: FIRSTAR BANK N.A.
Reel/Frame 010452/0624 →