IP Library › Assignment 009015/0336
Patent Assignment
Reel/Frame 009015/0336

Merger

Recorded: 1998-03-05 Pages: 13
Assignor
Assignee
ALTERA CORPORATION, A DELAWARE CORPORATION
101 INNOVATION DRIVE, SAN JOSE, CALIFORNIA, 95134
Covered Properties (108)
Programmable Logic Array Device Using Eprom Technology
Patent: 4,617,479 →
Application: 06/607,018 →
Programmable Logic Array Device Using Eprom Technology
Patent: 4,609,986 →
Application: 06/620,451 →
Programmable Logic Storage Element for Programmable Logic Devices
Patent: 4,677,318 →
Application: 06/722,684 →
Programmable Macrocell Using Eprom or Eeprom Transistors for Architecture Control in Programmable Logic Circuits
Patent: 4,713,792 →
Application: 06/742,089 →
Programmable Logic Array Device Using Eprom Technology
Patent: 4,774,421 →
Application: 06/907,075 →
Programmable Integrated Circuit Logic Array Device Having Improved Microprocessor Connectability
Patent: 4,969,121 →
Application: 07/020,556 →
Programmable Integrated Circuit Micro-Sequencer Device
Patent: 4,831,573 →
Application: 07/023,054 →
Multifunction Flip-Flop-Type Circuit
Patent: 4,864,161 →
Application: 07/190,530 →
Programmable Logic Device with Programmable Word Line Connections
Patent: 4,903,223 →
Application: 07/190,571 →
Programmable Logic Device with Array Blocks Connected via Programmable Interconnect
Patent: 4,871,930 →
Application: 07/190,663 →
Bit Line Sense Amplifier for Programmable Logic Devices
Patent: 4,899,070 →
Application: 07/218,556 →
Programmable Interface for Computer System Peripheral Circuit Card
Patent: 5,111,423 →
Application: 07/222,565 →
Programmable Logic Devices with Spare Circuits for Use in Replacing Defective Circuits
Patent: 4,899,067 →
Application: 07/222,832 →
Method and Apparatus for Programming and Verifying Programmable Elements in Programmable Devices
Patent: 4,930,107 →
Application: 07/229,852 →
Architecture for an Improved Performance of a Programmable Logic Device
Patent: 4,930,097 →
Application: 07/292,464 →
Programmable Logic Device with Array Blocks with Programmable Clocking
Patent: 4,912,342 →
Application: 07/407,411 →
Integrated Circuits with Reduced Switching Noise
Patent: 5,066,873 →
Application: 07/444,993 →
Methods and Apparatus for Reducing Coupling Noise in Programmable Logic Devices
Patent: 5,091,661 →
Application: 07/587,075 →
Reference Voltage Generator
Patent: 5,045,772 →
Application: 07/591,363 →
Sense Amplifier with Increased Speed and Reduced Power Consumption
Patent: 5,128,565 →
Application: 07/596,764 →
Methods and Apparatus for Facilitatiang Scan Testing of Asynchronous Logic Circuitry
Patent: 5,166,604 →
Application: 07/611,974 →
Apparatus and Method for Measuring Gate Delays in Integrated Circuit Wafers
Patent: 5,097,208 →
Application: 07/622,615 →
Registered Logic Macrocell with Product Term Allocation and Adjacent Product Term Stealing
Patent: 5,121,006 →
Application: 07/688,252 →
High-Density Erasable Programmable Logic Device Architecture Using Multiplexer Interconnections
Patent: 5,241,224 →
Application: 07/691,640 →
Complementary Low Power Non-Volatile Reconfigurable Eecell
Patent: 5,272,368 →
Application: 07/698,084 →
Zero Power, High Impedance Ttl-to-Cmos Converter
Patent: 5,144,167 →
Application: 07/701,686 →
Methods for Allocating Circuit Elements Between Circuit Groups
Patent: 5,341,308 →
Application: 07/702,001 →
Method of Programming Floating Gate Memory Devices Aided by Potential Applied to Read Channel
Patent: 5,247,477 →
Application: 07/708,241 →
Programmable Logic Element Interconnections for Programmable Logic Array Integrated Circuits
Patent: 5,260,610 →
Application: 07/754,017 →
Method for Programming Programmable Elements in Programmable Devices
Patent: 5,200,920 →
Application: 07/759,944 →
Method and Apparatus for Erasing an Array of Electrically Erasable Eprom Cells
Patent: 5,138,576 →
Application: 07/788,606 →
Method and Apparatus for Preventing Overerasure in a Flash Cell
Patent: 5,220,533 →
Application: 07/788,607 →
Sense Amplifier for Programmable Logic Device
Patent: 5,162,680 →
Application: 07/808,593 →
Stethoscope Cover
Patent: 5,269,314 →
Application: 07/818,346 →
Programmable Transfer-Devices
Patent: 5,247,478 →
Application: 07/846,915 →
Eeprom-Backed Fifo Memory
Patent: 5,353,248 →
Application: 07/868,174 →
Reduced Noise Output Buffer
Patent: 5,315,172 →
Application: 07/868,399 →
Surface Mount Chip Carrier
Patent: 5,301,416 →
Application: 07/874,281 →
Registered Logic Macrocell with Product Term Allocation and Adjacent Product Term Stealing
Patent: 5,220,214 →
Application: 07/879,908 →
Look Up Table Implementation of Fast Carry for Adders and Counters
Patent: 5,274,581 →
Application: 07/880,752 →
Programmable Logic Array Integrated Circuits with Cascade Connections Between Logic Modules
Patent: 5,258,668 →
Application: 07/880,888 →
Methods and Apparatus for Programming Cellular Programmable Logic Integrated Circuits
Patent: 5,237,219 →
Application: 07/880,908 →
Programmable Logic Array Having Local and Long Distance Conductors
Patent: 5,260,611 →
Application: 07/880,942 →
Gull Wing Ic Carrier/Socket System
Patent: 5,266,037 →
Application: 07/882,808 →
Look-Ahead Asynchronous Register Set/Reset in Programmable Logic Device
Patent: 5,280,203 →
Application: 07/883,100 →
Apparatus for Faciliting Scan Testing of Asynchronous Logic Circuitry
Patent: 5,285,153 →
Application: 07/947,729 →
Power on Reset Circuit Having Operational Voltage Trip Point
Patent: 5,243,233 →
Application: 07/950,345 →
Laser Alignment Target for Semiconductor Integrated Circuits
Patent: 5,294,975 →
Application: 07/961,598 →
Computer Logic Simulation with Dynamic Modeling
Patent: 5,477,474 →
Application: 07/969,943 →
Programmable Logic Devices with Spare Circuits for Replacement of Defects
Patent: 5,434,514 →
Application: 07/979,003 →
Clock Invert and Select Circuit
Patent: 5,341,048 →
Application: 07/981,442 →
Programmable Logic with Carry-in/Carry-Out Between Logic Blocks
Patent: 5,359,242 →
Application: 08/006,321 →
I/O Cell for Programmable Logic Device Providing Latched, Unlatched, and Fast Inputs
Patent: 5,317,210 →
Application: 08/021,414 →
Two-Transistor Flash Eprom Cell
Patent: 5,329,487 →
Application: 08/028,042 →
Programmable Tco Circuit
Patent: 5,349,255 →
Application: 08/028,092 →
Programmable Logic Device Having Multiplexers and Demultiplexers Randomly Connected to Global Conductors for Interconnections Between Logic Elements
Patent: 5,371,422 →
Application: 08/038,787 →
Macrocell with Flexible Product Term Allocation
Patent: 5,350,954 →
Application: 08/039,927 →
Programmable Logic Device with Multiplexer-Based Programmable Interconnections
Patent: 5,376,844 →
Application: 08/039,944 →
High-Density Erasable Programmable Logic Device Architecture Using Multiplexer Interconnections
Patent: 5,268,598 →
Application: 08/043,146 →
Flexible Configuration Logic Array Block for Programmable Logic Devices
Patent: 5,341,044 →
Application: 08/049,064 →
Fast Ttl to Cmos Level Converting Buffer with Low Standby Power
Patent: 5,359,243 →
Application: 08/049,694 →
Ram Convertible Look-Up Table Based Macrocell for Plds
Patent: 5,352,940 →
Application: 08/068,368 →
Look-Up Table Using Multi-Level Decode
Patent: 5,438,295 →
Application: 08/076,712 →
Macrocell Comprised of Two Look-Up Tables and Two Flip-Flops
Patent: 5,399,922 →
Application: 08/086,420 →
Pld with Selective Inputs from Local and Global Conductors
Patent: 5,444,394 →
Application: 08/088,973 →
Advanced Signal Driving Buffer with Directional Input Transition Detection
Patent: 5,414,312 →
Application: 08/092,350 →
High Voltage Driver Circuit with Fast Current Limiting for Testing of Integrated Circuits
Patent: 5,493,519 →
Application: 08/107,385 →
Programmable Logic Array Integrated Circuits
Patent: 5,436,575 →
Application: 08/111,693 →
High-Density Erasable Programmable Logic Device Architecture Using Multiplexer Interconnections
Patent: 5,384,499 →
Application: 08/123,435 →
Implementation of Redundancy on a Programmable Logic Device
Patent: 5,498,975 →
Application: 08/147,601 →
Unerasable Electronic Programmable Read Only Memory (Upromtm)
Patent: 5,525,827 →
Application: 08/148,059 →
Universal Logic Module with Arithmetic Capabilities
Patent: 5,436,574 →
Application: 08/153,321 →
Programmable Logic Device Having a Compressed Configuration File and Associasted Decompression
Patent: 5,563,592 →
Application: 08/156,561 →
Process Oriented Logic Simulation Having Stability Checking
Patent: 5,490,266 →
Application: 08/192,185 →
Universal Reconfigurable Printed Circuit Board
Patent: 5,537,295 →
Application: 08/206,774 →
Method and Apparatus for Assigning and Analyzing Timing Specifications in a Computer Aided Engineering Program
Patent: 5,572,717 →
Application: 08/223,914 →
Computer User Interface Having Tiled and Overlapped Window Areas
Patent: 5,487,143 →
Application: 08/223,930 →
Method and Apparatus for Enhanced Eprom and Eeprom Programmability and Process Scaling
Patent: 5,493,526 →
Application: 08/227,500 →
Programmable Logic Array Integrated Circuits
Patent: 5,550,782 →
Application: 08/245,509 →
Circuit for Reducing Ground Bounce
Patent: 5,604,453 →
Application: 08/301,511 →
Reconfigurable Programmable Logic Device Having Static and Non-Volatile Memory
Patent: 5,548,228 →
Application: 08/314,012 →
Sacrificial Corner Structures
Patent: 5,572,067 →
Application: 08/318,920 →
Method of Programming an Asynchronous Load Storage Device Using a Representation of a Clear/Preset Storage Device
Patent: 5,649,163 →
Application: 08/319,333 →
Method and Apparatus for Creating a Large Delay in a Pulse in a Layout Efficient Manner
Patent: 5,606,276 →
Application: 08/319,381 →
Programmable Logic Device with Low Power Voltage Level Translator
Patent: 5,432,467 →
Application: 08/324,312 →
Programmable Logic Device Having Fast Programmable Logic Array Blocks and a Central Global Interconnect Array
Patent: 5,473,266 →
Application: 08/324,860 →
Method and Apparatus for Erasing an Array of Electrically Erasable Programmable Read Only Memory Cells
Patent: 5,488,586 →
Application: 08/328,303 →
Eeprom Verification Circuit with Pmos Transistors
Patent: 5,550,842 →
Application: 08/330,761 →
Expanded Programmable Logic Architecture
Patent: 5,463,328 →
Application: 08/337,579 →
Baseboard and Daughtercard Apparatus for Reconfigurable Computing Systems
Patent: 5,583,749 →
Application: 08/348,280 →
Method of Forming a Dynamic Random Access Memory
Patent: 5,656,528 →
Application: 08/353,788 →
Surface Mount Chip Carrier
Patent: 5,567,177 →
Application: 08/381,005 →
High-Density Programmable Logic Device in a Multichip Module Package with Improved Interconnect Scheme
Patent: 5,642,262 →
Application: 08/393,576 →
Fast-Fully Restoring Polarity Control Circuit
Patent: 5,495,182 →
Application: 08/395,733 →
High Speed, Low Power Macrocell
Patent: 5,523,706 →
Application: 08/401,046 →
Programmable Logic Array Integrated Circuit Incorporating a First-in First-Out Memory
Patent: 5,570,040 →
Application: 08/408,504 →
Programmable Logic Array Integrated Circuit with General-Purpose Memory Configurable as a Random Acces or Fifo Memory
Patent: 5,572,148 →
Application: 08/408,510 →
Power-On Reset Circuit with Hysteresis
Patent: 5,612,642 →
Application: 08/430,923 →
Reconfigurable Programmable Logic Device
Patent: 5,548,552 →
Application: 08/457,884 →
Method and Apparatus of Testing an Integrated Circuit Device
Patent: 5,608,337 →
Application: 08/481,744 →
Programmable Logic Array Integrated Circuits with Enhanced Output Routing
Patent: 5,606,266 →
Application: 08/497,504 →
Method and Apparatus for Checking the Integrity of a Device Tester-Handler Setup
Patent: 5,621,312 →
Application: 08/498,190 →
Computer Logic Simulation
Patent: 5,574,893 →
Application: 08/512,600 →
Nonvolatile Sram Cells and Cell Arrays
Patent: 5,581,501 →
Application: 08/516,061 →
Computer User Interface Having Tiled and Overlapped Window Areas
Patent: 5,561,757 →
Application: 08/530,922 →
Dynamic Nonvolatile Memory Cell
Patent: 5,729,495 →
Application: 08/536,026 →
Programming Circuits and Techniques for Programming Logic
Patent: 5,590,305 →
Application: 08/572,806 →
Programmable Logic Array Integrated Circuits
Patent: 5,668,771 →
Application: 08/655,870 →
Related Assignments (24)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. May 3, 1984
From: HARTMANN, ROBERT F.; WONG, SAU-CHING; CHAN, YIU-FAI; OU, JUNG-HSING
To: ALTERA SEMICONDUCTOR CORP. 1723 HAMILTON AVENUE, SAN JOSE CALIFORNIA 95125 A CORP OF CA
Reel/Frame 004256/0809 →
Assignment of Assignors Interest. Jun 14, 1984
From: HARTMANN, ROBERT F.; CHAN, YIU-FAI; FRANKOVICH, ROBERT; OU, JUNG-HSING
To: ALTERA SEMICONDUCTOR CORPORATION 1723 HAMILTON AVE., SAN JOSE, CA 95125 A CORP. OF
Reel/Frame 004275/0748 →
Assignment of Assignors Interest. Apr 12, 1985
From: VEENSTRA, KERRY S.
To: ALTERA CORPORATON A CORP OF CA
Reel/Frame 004397/0485 →
Assignment of Assignors Interest. Jun 6, 1985
From: HARTMANN, ROBERT F.; CHAN, YIU-FAI; FRANKOVICH, ROBERT J.; OU, JUNG-HSING
To: ALTERA CORPORATION 3525 MONROE STREET, SANTA CLARA CA 95051 A CORP OF CA
Reel/Frame 004414/0853 →
Change of Name Effective 10/23/84 May 15, 1986
From: ALTERA SEMICONDUCTOR CORPORATION
To: ALTERA CORPORATION
Reel/Frame 004545/0720 →
Assignment of Assignors Interest. May 5, 1988
From: NORMAN, KEVIN A.; SO, HOCK-CHUEN; VEENSTRA, KERRY S.; WONG, SAU-CHING
To: ALTERA CORPORATION
Reel/Frame 004893/0587 →
Assignment of Assignors Interest. May 5, 1988
From: NORMAN, KEVIN A.; FRANKOVICH, ROBERT J.
To: ALTERA CORPORATION
Reel/Frame 004899/0450 →
Assignment of Assignors Interest. May 5, 1988
From: WONG, SAU-CHING; SO, HOCK-CHUEN; KOPEC, STANLEY J. JR.; HARTMANN, ROBERT F.
To: ALTERA CORPORATION, A CORP. OF CA
Reel/Frame 004881/0919 →
Assignment of Assignors Interest. Jul 13, 1988
From: OU, JUNG-HSING; WONG, SAU-CHING
To: ALTERA CORPORATION
Reel/Frame 004910/0678 →
Assignment of Assignors Interest. Jul 21, 1988
From: KOPEC, STANLEY J. JR.; CHAN, YIU-FAI; HARTMANN, ROBERT F.
To: ALTERA CORPORATION, 3525 MONROE STREET, SANTA CLARA, CA. 95051, A CORP. OF CA.
Reel/Frame 004914/0978 →
Assignment of Assignors Interest. Jul 22, 1988
From: SO, HOCK-CHUEN; WONG, SAU-CHING
To: ALTERA CORPORATION, 3525 MONROE STREET, SANTA CLARA, CALIFORNIA 95051 A CORP. OF CA
Reel/Frame 004926/0847 →
Assignment of Assignors Interest. Aug 8, 1988
From: CHAN, YIU-FAI; HUNG, CHUAN-YUNG
To: ALTERA CORPORATION, 3525 MONOROE STREET, SANTA CLARA, CALIFORNIA 95051, A CORP. OF CA
Reel/Frame 004916/0904 →
Assignment of Assignors Interest. Dec 30, 1988
From: LEDENBACH, GREGORY W.; ALLEN, MICHAEL J.
To: INTEL CORPORATION
Reel/Frame 004999/0704 →
Assignment of Assignors Interest. Oct 30, 1989
From: WONG, SAU-CHING; SO, HOCK-CHUEN; KOPEC, STANLEY J. JR.; HARTMANN, ROBERT F.
To: ALTERA CORPORATION
Reel/Frame 005173/0117 →
Assignment of Assignors Interest. Dec 4, 1989
From: CHAN, YIU-FAI; HSIAO, CHANG-CHIA; WATSON, JAMES A.
To: ALTERA CORPORATION, 3525 MONROE STREET, SANTA CLARA, CA 95051 A CORP. OF CA
Reel/Frame 005188/0316 →
Assignment of Assignors Interest. Sep 24, 1990
From: CHIANG, DAVID
To: ALTERA CORPORATION
Reel/Frame 005460/0693 →
Assignment of Assignors Interest. Oct 1, 1990
From: NISHIWAKI, KUNIO; NORMAN, KEVIN A.
To: ALTERA CORPORATION
Reel/Frame 005470/0159 →
Assignment of Assignors Interest. Nov 13, 1990
From: AHANIN, BAHRAM; LYTLE, CRAIG S.; HO, RICKY W.
To: ALTERA CORPORATION
Reel/Frame 005507/0905 →
Assignment of Assignors Interest. Dec 5, 1990
From: CHIANG, DAVID
To: ALTERA CORPORATION
Reel/Frame 005532/0498 →
Assignment of Assignors Interest. Jan 7, 1991
From: MC CLINTOCK, CAMERON; SO, HOCK C.
To: ALTERA CORPORATION, A CORP. OF CA
Reel/Frame 005557/0309 →
Assignment of Assignors Interest. Apr 22, 1991
From: PEDERSEN, BRUCE B.
To: ALTERA CORPORATION
Reel/Frame 005692/0245 →
Assignment of Assignors Interest. May 10, 1991
From: TURNER, JOHN E.; CLIFF, RICHARD G.
To: ALTERA CORPORATION
Reel/Frame 005705/0707 →
Assignment of Assignors Interest. Jul 1, 1991
From: PEDERSEN, BRUCE B.; CHIANG, DAVID; HEILE, FRANCIS B.; MCCLINTOCK, CAMERON
To: ALTERA CORPORATION, A CORPORATION OF CA
Reel/Frame 005755/0785 →
Merger Nov 12, 1997
From: ALTERA CORPORATION (A CORPORATION OF CALIFORNIA)
To: ALTERA CORPORATION (A CORPORATION OF DELAWARE)
Reel/Frame 008811/0577 →