IP Library › Assignment 010927/0853
Patent Assignment
Reel/Frame 010927/0853

Assignment of Assignor's Interest

Recorded: 2000-06-28 Pages: 25
Assignor
CRAY RESEARCH, L.L.C.
Executed: 2000-05-24
Assignee
SILICON GRAPHICS, INC.
M/S 6L-710, 1600 AMPHITHEATRE PARKWAY, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties (195)
Title Not Available
Application: 05/702,148 →
Floating Point Data Processor
Patent: 4,179,734 →
Application: 05/846,889 →
Instruction Cache Memory System
Patent: 4,442,488 →
Application: 06/468,506 →
Computer Vector Multiprocessing Control
Patent: 4,636,942 →
Application: 06/488,082 →
Direct-Execution Microprogrammable Microprocessor System
Patent: 4,761,733 →
Application: 06/710,615 →
System for Multiprocessor Communication Using Local and Common Semaphore and Information Registers
Patent: 4,754,398 →
Application: 06/750,487 →
Flexible Chaining in Vector Processor with Selective Use of Vector Registers as Operand and Result Registers
Patent: 4,661,900 →
Application: 06/858,862 →
Zif Edge Connector
Patent: 4,700,996 →
Application: 06/916,509 →
Data Modulation Interface
Patent: 4,771,440 →
Application: 06/937,374 →
Massively Parallel Vector Processing Computer
Patent: 4,891,751 →
Application: 07/031,697 →
Lead Bonding of Chips Onto Boards and Circuit Boards to Circuit Boards
Patent: 5,054,192 →
Application: 07/053,142 →
Gallium Arsenide Depletion Mode Mesfet Logic Cell
Patent: 4,965,863 →
Application: 07/104,758 →
Peripheral Interface System
Patent: 4,807,121 →
Application: 07/205,533 →
Computer Vector Multiprocessing Control with Multiple Access Memory and Priority Conflict Resolution Method
Patent: 4,901,230 →
Application: 07/208,809 →
Parallel Board Zif Module Connector
Patent: 4,911,645 →
Application: 07/284,905 →
Wire/Disk Board-to-Board Interconnect Device
Patent: 4,859,188 →
Application: 07/306,229 →
Method and Apparatus for Cooling an Integrated Circuit Chip During Testing
Patent: 4,982,153 →
Application: 07/307,259 →
System for Multiprocessor Communication
Patent: 5,526,487 →
Application: 07/308,401 →
Reduced Capacitance Chip Carrier
Patent: 5,134,247 →
Application: 07/313,395 →
Cam Actuated Electrical Connector
Patent: 4,975,074 →
Application: 07/315,124 →
Linear Nearest Neighbor Interconnect Bus System
Patent: 5,003,508 →
Application: 07/338,557 →
Twisted Wire Jumper Electrical Interconnector and Method of Mailing
Patent: 5,014,419 →
Application: 07/347,507 →
Two-Piece Edge Zif Connector with Sliding Block
Patent: 4,984,993 →
Application: 07/351,871 →
Modular Input/Output System for Supercomputers
Patent: 5,347,637 →
Application: 07/390,722 →
Read-While-Write Ram Cell
Patent: 4,964,081 →
Application: 07/393,528 →
High Power, High Density Interconnect Method and Apparatus for Integrated Circuits
Patent: 5,127,986 →
Application: 07/444,747 →
Miniature Controlled-Impedance Transmission Line Cable and Method of Manufacture
Patent: 5,015,800 →
Application: 07/454,022 →
Cluster Architecture for a Highly Parallel Scalar/Vector Mulriprocessor System
Patent: 5,197,130 →
Application: 07/459,083 →
Air Jet Impingement on Miniature Pin-Fin Heat Sinks for Cooling Electronic Components
Patent: 5,083,194 →
Application: 07/465,042 →
Skew-Compensated Clock Distribution System
Patent: 5,258,660 →
Application: 07/465,947 →
Parallel Processing System for Matrix Calculation
Patent: 5,081,573 →
Application: 07/469,818 →
Method of Fabricating Metallized Chip Carriers Form Wafer-Shaped Substrates
Patent: 5,182,420 →
Application: 07/506,729 →
Method and Apparatus for Sharing Memory in a Multiprocessor System
Patent: 5,247,637 →
Application: 07/531,861 →
Method and Apparatus for Non-Sequential Resource Access
Patent: 5,208,914 →
Application: 07/535,786 →
Vertical Semiconductor Interconnection Method and Structure
Patent: 5,041,903 →
Application: 07/535,837 →
Control and Maintenance Subsystem Network for Use with a Multiprocessor Computer System
Patent: 5,253,359 →
Application: 07/535,901 →
Distributed Architecture for Input/Output for a Multiprocessor System
Patent: 5,168,547 →
Application: 07/536,182 →
Dedicated Centralized Signaling Mechanism for Selectively Signaling Devices in a Multiprocessor System
Patent: 5,239,629 →
Application: 07/536,192 →
Method and Apparatus for a Special Purpose Arithmetic Boolean Unit
Patent: 5,175,862 →
Application: 07/536,197 →
Global Registers for a Multiprocessor System
Patent: 5,165,038 →
Application: 07/536,198 →
Clock Distribution Apparatus and Processes Using Electrical and Optical Delay Lines Particularly Useful in Multiprocessor Systems
Patent: 5,293,626 →
Application: 07/536,270 →
Packaging Architecture for a Highly Parallel Multiprocessor System
Patent: 5,251,097 →
Application: 07/536,395 →
Scalar/Vector Processor
Patent: 5,430,884 →
Application: 07/536,409 →
Method and Apparatus for a Multiple Request Toggling Priority System
Patent: 5,168,570 →
Application: 07/536,417 →
System and Method for Controlling a Highly Parallel Multiprocessor Using an Anarchy Based Scheduler for Parallel Execution Thread Scheduling
Patent: 5,179,702 →
Application: 07/537,466 →
Flexible Automated Bonding Method and Apparatus
Patent: 5,127,570 →
Application: 07/545,271 →
Computer Signal Interconnect Apparatus
Patent: 5,144,691 →
Application: 07/556,031 →
Method and Apparatus for Single Step Clocking on Signal Paths Longer Than a Clock Cycle
Patent: 5,055,707 →
Application: 07/568,169 →
Vectorized Lr Parsing of Computer Programs
Patent: 5,193,192 →
Application: 07/571,502 →
Method for Representing Scalar Data Dependences for an Optimizing Compiler
Patent: 5,107,418 →
Application: 07/571,503 →
System for Communicating Among Processors Having Different Speeds
Patent: 5,202,988 →
Application: 07/571,951 →
Computer with Integrated Hierarchical Reprsentation (Ihr) of Program Wherein Ihr File Is Available for Debugging and Optimizing During Target Execution
Patent: 5,175,856 →
Application: 07/572,043 →
Method for Efficient Non-Virtual Main Memory Management
Patent: 5,159,678 →
Application: 07/572,045 →
Dual Contact Beam Assembly for an Ic Test Fixture
Patent: 5,175,496 →
Application: 07/575,935 →
Fault Tolerant Networking Architecture
Patent: 5,206,952 →
Application: 07/582,507 →
High Power, High Density Interconnect Apparatus for Integrated Circuits
Patent: 5,185,502 →
Application: 07/598,103 →
Vector Bit-Matrix Multiply Functional Unit
Patent: 5,170,370 →
Application: 07/616,736 →
Methods for Efficient Distribution of Parallel Tasks to Slave Processes in a Multiprocessing System
Patent: 5,257,372 →
Application: 07/630,301 →
Graphical Display of Compiler-Generated Intermediate Database Representation
Patent: 5,187,789 →
Application: 07/640,909 →
Method for Compiling Loops Having Recursive Equations by Detecting and Correcting Recurring Data Points Before Storing the Result to Memory
Patent: 5,247,696 →
Application: 07/642,480 →
System for Distributed Multiprocessor Communication
Patent: 5,434,970 →
Application: 07/655,296 →
Air Jet Impinmgement on Miniature Pin-Fin Heat Sinks for Cooling Electronic Components
Patent: 5,166,775 →
Application: 07/664,940 →
Apparatus for Sharing Memory in a Multiprocessor System
Patent: 5,142,638 →
Application: 07/682,876 →
Apparatus for Calculating Delay When Executing Vector Tailgating Instructions and Using Delay to Facilitate Simultaneous Reading of Operands from and Writing of Results to Same Vector Register
Patent: 5,349,677 →
Application: 07/683,095 →
Transmission Line with Fluid-Permeable Jacket
Patent: 5,142,100 →
Application: 07/694,467 →
Method and Apparatus for Laser Masking of Lead Bonding
Patent: 5,194,710 →
Application: 07/704,067 →
Method of Manufacturing Interconnect Bumps
Patent: 5,283,948 →
Application: 07/708,447 →
Memory Range Monitoring Apparatus for a Multiprocessor Computer System
Patent: 5,295,260 →
Application: 07/708,461 →
Metallized Connector Block
Patent: 5,211,567 →
Application: 07/725,007 →
Single Disk Emulation Interface for an Array of Synchronous Spindle Disk Drives
Patent: 5,128,810 →
Application: 07/727,282 →
Method of Fabricating Silicon-Based Carriers
Patent: 5,196,377 →
Application: 07/747,523 →
Fiber Optic Channel Extender Interface Method and Apparatus
Patent: 5,390,041 →
Application: 07/788,496 →
A Parallel Vector Processing System for Individual and Braodcast Distribution of Operands and Control Information
Patent: 5,226,171 →
Application: 07/802,643 →
Clock Pulse Measuring and Deskewing System and Process
Patent: 5,329,188 →
Application: 07/803,926 →
Distributing System for Multi-Processor Input and Output Using Channel Adapters
Patent: 5,388,217 →
Application: 07/807,082 →
Optimization of Alternate Loop Exits
Patent: 5,361,354 →
Application: 07/809,390 →
Integrated Circuit Chip Carrier Lid
Patent: 5,258,576 →
Application: 07/816,967 →
Method for Sharing Memory in a Multiprocessor System
Patent: 5,202,970 →
Application: 07/834,867 →
Multilayer Interconnect System for an Area Array Interconnection Using Solid State Diffusion
Patent: 5,276,955 →
Application: 07/868,531 →
Method of Fabricating Metallized Chip Carriers from Wafer-Shaped Substrates
Patent: 5,358,826 →
Application: 07/884,285 →
Solid State Storage Device
Patent: 5,321,697 →
Application: 07/890,026 →
Method for Optimizing Instruction Scheduling for a Processor Having Multiple Functional Resources
Patent: 5,202,975 →
Application: 07/896,895 →
Single Disk Emulation Interface for an Array of Asynchronously Operating Disk Drives
Patent: 5,218,689 →
Application: 07/897,600 →
Fast Interrupt Mechanism for a Interrupting Processors in Parallel in a Multiprocessor System Wherein Processors Are Assigned Process Id Numbers
Patent: 5,193,187 →
Application: 07/898,387 →
Method and Apparatus for a Unified Parallel Processing Architecture
Patent: 5,428,803 →
Application: 07/912,964 →
High Performance Mantissa Divider
Patent: 5,258,944 →
Application: 07/938,715 →
Clock Start Up Stabilization for Computer Systems
Patent: 5,355,397 →
Application: 07/950,628 →
Method for Inserting a Path Instruction During Compliation of Comuter Programs for Processors Having Multiple Functional Units
Patent: 5,307,478 →
Application: 07/969,789 →
Dual Level Scheduling of Processes to Multiple Parallel Regions of a Multi-Threaded Program on a Tightly Coupled Multiprocessor Computer System
Patent: 5,339,415 →
Application: 07/973,598 →
Apparatus for Cooling Daughter Boards
Patent: 5,343,359 →
Application: 07/983,086 →
Direction Order Priority Routing of Packets Between Nodes in a Networked System
Patent: 5,533,198 →
Application: 07/983,979 →
Method and Apparatus for User Side Scheduling in a Multiprocessor Operating System Program That Implements Distributive Scheduling of Processes
Patent: 6,195,676 →
Application: 08/003,000 →
Synchronized Stereoscopic Display System
Patent: 5,245,319 →
Application: 08/013,165 →
Optical Clock Distribution System
Patent: 5,537,498 →
Application: 08/027,049 →
Error Recovery Method and Apparatus for High Performance Disk Drives
Patent: 5,283,791 →
Application: 08/033,423 →
Method for Use in Designing an Arbitrarily Shaped Object
Patent: 5,453,934 →
Application: 08/038,143 →
Printed Circuit Board with Cooling Monitoring System
Patent: 5,281,026 →
Application: 08/056,650 →
System Having Integrated Dispatcher for Self Scheduling Processors to Execute Multiple Types of Processes
Patent: 5,452,452 →
Application: 08/072,655 →
Method for Adjusting Clock Skew
Patent: 5,467,040 →
Application: 08/098,204 →
Method of Adjusting for Clock Skew
Patent: 5,414,381 →
Application: 08/098,503 →
Multiprocessing System Using Indirect Addressing to Access Respective Local Semaphore Registers Bits for Setting the Bit or Branching If the Bit Is Set
Patent: 5,367,690 →
Application: 08/129,437 →
Method and Apparatus for Locking Shared Memory Locations in Multiprocessing Systems
Patent: 5,535,365 →
Application: 08/141,259 →
Configurable Spare Memory Chips
Patent: 5,392,292 →
Application: 08/149,967 →
System and Method of Addressing Distributed Memory Within a Massively Parallel Processing System
Patent: 5,765,181 →
Application: 08/165,118 →
Barrier Synchronization for Distributed Memory Massively Parallel Processing Systems
Patent: 5,434,995 →
Application: 08/165,265 →
System for Allocating Messages Between Virtual Channels to Avoid Deadlock and to Optimize the Amount of Message Traffic on Each Type of Virtual Channel
Patent: 5,583,990 →
Application: 08/165,266 →
Method for the Dynamic Allocation of Array Sizes in a Multiprocessor System
Patent: 5,586,325 →
Application: 08/165,379 →
Recursive Address Centrifuge for Distributed Memory Massively Parallel Processing Systems
Patent: 5,696,922 →
Application: 08/165,388 →
Repetitive Signal Detector for Preventing Thermal Runaway
Patent: 5,418,481 →
Application: 08/165,747 →
Virtual to Logical to Physical Address Translation for Distributed Memory Massively Parallel Processing Systems
Patent: 5,784,706 →
Application: 08/165,814 →
Method of Managing Distributed Memory Within a Massively Parallel Processing System
Patent: 5,566,321 →
Application: 08/166,293 →
Messaging Facility with Hardware Tail Pointer and Software Implemented Head Pointer Message Queue for Distributed Memory Massively Parallel Processing System
Patent: 5,581,705 →
Application: 08/166,443 →
Method for the Dynamic Allocation of Page Sizes in Virtual Memory
Patent: 5,802,341 →
Application: 08/166,451 →
Method and Apparatus for a Multiprocessor Resource Lockout Instruction
Patent: 5,499,356 →
Application: 08/173,923 →
Real Time I/O Operation in a Vector Processing Computer System by Running Designated Processors in Privileged Mode and Bypass the Operating System
Patent: 5,390,300 →
Application: 08/200,921 →
Vector Shift Functional Unit for Successively Shifting Operands Stored in a Vector Register by Corresponding Shift Counts Stored in Another Vector Register
Patent: 5,481,746 →
Application: 08/218,997 →
Optical Clock Distribution Method and Apparatus
Patent: 5,442,475 →
Application: 08/231,996 →
Apparatus and Method for Testing of New Operating Systems Through Privileged Instruction Trapping
Patent: 5,371,879 →
Application: 08/233,222 →
Method and Apparatus for Separate Mark and Wait Instructions for Processors Having Multiple Memory Ports
Patent: 5,381,536 →
Application: 08/249,084 →
Interleaved Memory Access System Having Variable-Sized Segments Logical Address Spaces and Means for Dividing/Mapping Physical Address into Higher and Lower Order Addresses
Patent: 5,561,784 →
Application: 08/268,660 →
Responding to Service Requests Using Minimal System-Side Context in a Multiprocessor Environment
Patent: 5,390,329 →
Application: 08/277,776 →
Extendible Clock Mechanism
Patent: 5,625,831 →
Application: 08/331,730 →
Stream Buffers for High-Performance Computer Memory Systems
Patent: 5,761,706 →
Application: 08/333,133 →
Apparatus and Method for Testing Using Clocked Test Access Port Controller for Level Sensitive Scan Designs
Patent: 6,173,428 →
Application: 08/340,238 →
Outer Loop Vectorization
Patent: 5,802,375 →
Application: 08/344,236 →
Associative Scalar Data Cache with Write-Through Capabilities for a Vector Processor
Patent: 5,717,895 →
Application: 08/348,056 →
Method and Apparatus for Accessing Global Registers in a Multiprocessor System
Patent: 5,524,255 →
Application: 08/379,123 →
Method and Apparatus for Chaining Vector Instructions
Patent: 5,640,524 →
Application: 08/395,320 →
Boundary Scan Testing Using Clocked Signal
Patent: 5,487,074 →
Application: 08/406,571 →
Communication Protocol for Transferring Information Across a #S Serial Communication Link
Patent: 5,592,487 →
Application: 08/407,808 →
Adaptive Routing Mechanism for Torus Interconnection Network
Patent: 5,701,416 →
Application: 08/421,566 →
System for Randomly Modifying Virtual Channel Allocation and Accepting the Random Modification Based on the Cost Function
Patent: 5,659,796 →
Application: 08/422,072 →
Barrier and Eureka Synchronization Architecture for Multiprocessors
Patent: 5,721,921 →
Application: 08/450,251 →
Vector Processor Having Functional Unit Paths of Differing Pipeline Lengths
Patent: 5,598,547 →
Application: 08/478,815 →
Data Processing System for Processing One and Two Parcel Instructions
Patent: 5,717,881 →
Application: 08/481,060 →
Method of Processing Conditional Branch Instructions in Scalar/Vector Processor
Patent: 5,706,490 →
Application: 08/484,103 →
Method of Processing a Sequence of Conditional Vector If Statements
Patent: 5,623,650 →
Application: 08/484,124 →
Partitioned Addressing Apparatus for Vector/Scalar Registers
Patent: 5,745,721 →
Application: 08/485,017 →
Vector/Scalar Processor with Simultaneous Processing and Instruction Cache Filling
Patent: 5,659,706 →
Application: 08/486,612 →
Vector Processor Having Registers for Control by Vector Registers
Patent: 5,544,337 →
Application: 08/487,952 →
Vector Word Shift by Vo Shift Count in Vector Supercomputer Processor
Patent: 5,848,286 →
Application: 08/521,566 →
Configuring of Networked System to Permit Replacement of Failed Nodes and Selection of Alternate Paths
Patent: 5,689,646 →
Application: 08/541,803 →
Virtual Maintenance Network in Multiprocessing System Having a Non- Flow Controlled Virtual Maintenance Channel
Patent: 6,055,618 →
Application: 08/550,992 →
Transparent Relocation of Real Memory Addresses in the Main Memory of a Data Processor
Patent: 5,765,198 →
Application: 08/595,528 →
Daughter Card Assembly
Patent: 5,761,043 →
Application: 08/604,839 →
Method and Apparatus for Cooling Daughter Card Modules
Patent: 5,801,924 →
Application: 08/604,888 →
Cooling Cap Method and Apparatus for Tab Packaged Integrated Circuits
Patent: 5,805,418 →
Application: 08/604,918 →
Cooling Approach for High Power Integrated Circuits Mounted on Printed Circuit Boards
Patent: 5,768,104 →
Application: 08/605,355 →
Massively Parallel Processing System Using Two Data Paths: One Connecting Router Circuit to the Interconnect Network and the Other Connecting Router Circuit to I/O Controller
Patent: 5,864,738 →
Application: 08/614,859 →
System and Method for Fault-Tolerant Transmission of Data Within a Dual Ring Network
Patent: 6,233,704 →
Application: 08/614,860 →
Using External Registers to Extend Memory Reference Capabilities of a Microprocessor
Patent: 5,835,925 →
Application: 08/615,671 →
Messaging in Distributed Memory Multiprocessing System Having Shell Circuitry for Atomic Control of Message Storage Queue's Tail Pointer Structure in Local Memory
Patent: 5,841,973 →
Application: 08/615,694 →
Adaptive Congestion Control Mechanism for Modular Computer Networks
Patent: 5,748,900 →
Application: 08/615,700 →
Raid-5 Parity Generation and Data Reconstruction
Patent: 5,805,788 →
Application: 08/650,336 →
Method and Apparatus for Adjusting the Power Supply Voltage Provided to a Microprocessor
Patent: 5,694,028 →
Application: 08/650,337 →
A System for Arbitrating Packetized Data from the Network to the Peripheral Resources and Prioritizing the Dispatching of Packets Onto the Network
Patent: 5,761,534 →
Application: 08/650,630 →
A Raid System Using I/O Buffer Segment to Temporary Store Striped and Parity Data and Connecting All Disk Drives via a Single Time Multiplexed Network
Patent: 5,862,313 →
Application: 08/650,632 →
Networked Multiprocessor System with Global Distributed Memory and Block Transfer Engine
Patent: 5,797,035 →
Application: 08/661,908 →
Multiprocessor Computer System with Interleaved Processing Element Nodes
Patent: 5,737,628 →
Application: 08/662,868 →
Method and Apparatus for Removing Power-of-Two Restrictions on Distributed Addressing
Patent: 5,900,023 →
Application: 08/673,436 →
Density Dependent Vector Mask Operation Control Apparatus and Method
Patent: 5,940,625 →
Application: 08/706,808 →
Embedding a Digital Signature in a Video Sequence
Patent: 5,960,081 →
Application: 08/869,792 →
Recursive Address Centrifuge for Distributed Memory Massively Parallel Processing Systems
Patent: 6,119,198 →
Application: 08/889,251 →
Precise Detection of Errors Using Hardware Watchpoint Mechanism
Patent: 5,987,626 →
Application: 08/920,177 →
Stop Align Lateral Module to Module Interconnect
Patent: 6,116,915 →
Application: 08/927,359 →
System and Method for Distributed Multiprocessor Communications
Patent: 5,920,714 →
Application: 08/927,507 →
Adaptive Bandwidth Sharing
Patent: 6,205,119 →
Application: 08/931,565 →
Demateable, Compliant, Area Array Interconnect
Patent: 6,142,789 →
Application: 08/934,973 →
Adaptive Congestion Control Mechanism for Modular Computer Networks
Patent: 5,958,017 →
Application: 08/935,667 →
Porous Metal Heat Sink
Patent: 6,018,459 →
Application: 08/971,179 →
Multiprocessor Computer System and Method for Maintaining Cache Coherence Utilizing a Multi-Demensional Cache Coherence Directory Structure
Patent: 6,633,958 →
Application: 08/971,184 →
Spacial Derivative Bus Encoder and Decoder
Patent: 6,480,548 →
Application: 08/971,185 →
Router Table Lookup Mechanism
Patent: 5,970,232 →
Application: 08/971,587 →
Hybrid Hypercube/Torus Architecture
Patent: 6,230,252 →
Application: 08/971,588 →
Virtual Channel Assignment in Large Torus Systems
Patent: 6,101,181 →
Application: 08/971,591 →
Serialized Race-Free Virtual Barrier Network
Patent: 6,085,303 →
Application: 08/972,010 →
Interleaving Memory in Distributed Vector Architecture Multiprocessor System
Patent: 5,913,069 →
Application: 08/987,948 →
Distributed Vector Architecture
Patent: 5,946,496 →
Application: 08/988,524 →
Message Buffering for a Computer-Based Network
Patent: 6,256,677 →
Application: 08/991,233 →
Method of Handling Arbitrary Size Message Queues in Which a Message Is Written into an Aligned Block of External Registers Within a Plurality of External Registers
Patent: 6,029,212 →
Application: 09/006,449 →
The Fabrication of Test Logic for Level Sensitive Scan on a Circuit
Patent: 6,092,226 →
Application: 09/021,651 →
Diamond-Based Transformers and Power Convertors
Patent: 6,181,231 →
Application: 09/055,554 →
System and for Stacking of Integrated Circuit Packages
Patent: 6,172,874 →
Application: 09/055,677 →
Large Area, Multi-Device Heat Pipe for Stacked Mcm-Based Systems
Patent: 6,055,157 →
Application: 09/056,037 →
Method and Apparatus for Processing a Set of Data Values with Plural Processing Units Using Mask Bits Generated by Other Processing Units
Patent: 6,308,250 →
Application: 09/103,201 →
Eigen-Mode Encoding of Signals in a Data Group
Patent: 6,226,330 →
Application: 09/118,158 →
Cooling Cap Method and Apparatus for Tab Packaged Integrated Circuit
Patent: 5,963,428 →
Application: 09/136,908 →
Vector Shift Functional Unit for Successively Shifting Operands Stored in a Vector Register by Corresponding Shift Counts Stored in Another Vector Register
Patent: 6,098,162 →
Application: 09/138,613 →
System and Method for Fast Barrier Synchronization
Patent: 6,216,174 →
Application: 09/162,673 →
Array Address and Loop Alignment Calculations
Patent: 6,128,639 →
Application: 09/174,862 →
High Performance Gas Cooling System and Method
Patent: 6,167,947 →
Application: 09/215,531 →
Method and Apparatus for Partial-Scan Built-in Self-Test Logic
Patent: 6,349,398 →
Application: 09/237,486 →
Floating-Point Adder Performing Floating-Point and Integer Operations
Patent: 6,529,928 →
Application: 09/274,595 →
Method for Determining the Optimum Locations for Scan Latches in a Partial-Scan Ic Built in Self Test System
Patent: 6,651,197 →
Application: 09/315,904 →
Age-Based Network Arbitration System and Method
Patent: 6,674,720 →
Application: 09/408,778 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Aug 1, 1983
From: CHEN, STEVE S.; SCHIFFLEGER, ALAN J.; SOMDAHL, EUGENE R.; HIGBIE, LEE
To: CRAY RESEARCH, INC.
Reel/Frame 004189/0931 →
Assignment of Assignors Interest. Mar 11, 1985
From: MC CROCKLIN, ANDREW J.; ANESHANSLEY, NICHOLAS E.; SHANAHAN, PATRICIA; WHELAN, JAMES J.
To: CELERITY COMPUTING
Reel/Frame 004389/0131 →
Assignment of Assignors Interest. Sep 13, 1985
From: PRIBNOW, RICHARD D.
To: CRAY RESEARCH, INC.
Reel/Frame 004456/0706 →
Assignment of Assignors Interest. Dec 10, 1987
From: CRAY, SEYMOUR R.
To: CRAY RESEARCH, INC., A CORP. OF DE.
Reel/Frame 004825/0688 →
Assignment of Assignors Interest. Dec 14, 1988
From: AUGUST, MELVIN C.; NEUMANN, EUGENE F.
To: CRAY RESEARCH, INC., A CORP. OF DE
Reel/Frame 005005/0899 →
Assignment of Assignors Interest. Feb 6, 1989
From: COLLINS, DAVID R.; FRANZ, PERRY D.; TAYLOR, PAMELA W.
To: CRAY RESEARCH, INC.
Reel/Frame 005039/0465 →
Assignment of Assignors Interest. Mar 27, 1989
From: KNUDSEN, PAUL M.; EBERLEIN, DELVIN D.
To: CRAY RESEARCH, INC., 608 2ND AVENUE SOUTH, MPLS, MN 55402, A CORP. OF MN
Reel/Frame 005057/0305 →
Assignment of Assignors Interest. Mar 27, 1989
From: LEONARD, DAVID F.; STEITZ, RICHARD R.
To: CRAY RESEARCH, INC., 608 2ND AVENUE SOUTH, MPLS, MN 55402, A CORP. OF MN
Reel/Frame 005057/0303 →
Assignment of Assignors Interest. Mar 27, 1989
From: DUXSTAD, DAVID L.; AUGUST, MELVIN C.
To: CRAY RESEARCH, INC., 608 2ND AVENUE SOUTH, MINNEAPOLIS, MN 55402, A CORP. OF MN
Reel/Frame 005057/0299 →
Assignment of Assignors Interest. Mar 27, 1989
From: WEHNER, PETER J.
To: CRAY RESEARCH, INC., 608 2ND AVENUE SOUTH MPLS, MN 55402, A CORP. OF MN
Reel/Frame 005057/0301 →
Assignment of Assignors Interest. Apr 24, 1989
From: SCHIFFLEGER, ALAN J.
To: CRAY RESEARCH, INC., CORP. OF DE
Reel/Frame 005065/0789 →
Assignment of Assignors Interest. Jun 12, 1989
From: CRAY, SEYMOUR R.; KRAJEWSKI, NICHOLAS J.
To: CRAY RESEARCH, INC., 608 SECOND AVENUE SOUTH, MINNEAPOLIS, MN 55402, ACORP. OF DE
Reel/Frame 005098/0612 →
Assignment of Assignors Interest. Jul 11, 1989
From: NEUMANN, EUGENE F.; AUGUST, MELVIN C.; BOWEN, STEPHEN A.
To: CRAY RESEARCH, INC., A CORP. OF WI.
Reel/Frame 005165/0491 →
Assignment of Assignors Interest. Aug 3, 1989
From: NEIDICH, DOUGLAS A.
To: INTERCON SYSTEMS, INC.
Reel/Frame 005149/0937 →
Assignment of Assignors Interest. Aug 3, 1989
From: NEIDICH, DOUGLAS A.
To: INTERCON SYSTEMS, INC.
Reel/Frame 005149/0933 →
Assignment of Assignors Interest. Aug 11, 1989
From: BIRRITTELLA, MARK S.; WIKSTROM, JAN A.
To: CRAY RESEARCH, INC., A CORP. OF DE
Reel/Frame 005112/0365 →
License Jan 22, 1990
From: INTERCON SYSTEMS, INC.
To: CRAY RESEARCH, INC.
Reel/Frame 005217/0728 →
Assignment of Assignors Interest. Apr 2, 1990
From: SHEPHERD, LLOYD T.; AUGUST, MELVIN C.; KRUCHOWSKI, JAMES N.
To: CRAY RESEARCH, INC.
Reel/Frame 005347/0482 →
Assignment of Assignors Interest. Apr 19, 1990
From: HALFORD, ROBERT J.
To: CRAY RESEARCH, INC.
Reel/Frame 005278/0805 →
Assignment of Assignors Interest. Apr 27, 1990
From: CRAY RESEARCH, INC.
To: CRAY COMPUTER CORPORATION
Reel/Frame 005287/0628 →
Assignment of Assignors Interest. May 7, 1990
From: CRAY RESEARCH, INC., A CORP. OF DE.
To: CRAY COMPUTER CORPORATION, A CORP. OF DE.
Reel/Frame 005327/0115 →
Assignment of Assignors Interest. Sep 28, 1990
From: HOPKINS, GEORGE M.; LOGGHE, PETER G.; LUNDBERG, ERIC P.; HALFORD, ROBERT J.
To: CRAY RESEARCH, INC.
Reel/Frame 005452/0987 →
Assignment of Assignors Interest. Oct 29, 1990
From: COLEMAN, CALVIN P.
To: CRAY RESEARCH, INC., 608 SECOND AVENUE SOUTH, A CORP OF MN
Reel/Frame 005485/0439 →
Assignment of Assignors Interest. Oct 8, 1992
From: FLOATING POINT SYSTEMS, INC.
To: RDM ACQUISITION CORPORATION
Reel/Frame 006294/0656 →
Change of Name Oct 8, 1992
From: RDM ACQUISITION CORPORATION
To: CRAY RESEARCH SUPERSERVERS, INC.
Reel/Frame 006294/0664 →