IP Library › Assignment 013506/0135

Patent Assignment

Reel/Frame 013506/0135

Change of Name

Recorded: 2002-11-13 Pages: 4

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Assignor

OASIS DESIGN, INCORPORATED

Executed: 2002-01-02

Assignee

OASIS SILICON SYSTEMS, INC.

1120 S. CAPITAL OF TEXAS HIGHWAY S., BUILDING II, SUITE 100, AUSTIN, TEXAS, 78746

Covered Properties (16)

Analog-To-Digital Converter with Local Feedback

Patent: 5,654,711 →

Application: 08/486,690 →

Pipelined Digital Signal Processor and Signal Processing System Employing Same

Patent: 5,826,072 →

Application: 08/558,636 →

Merged Multi-Stage Comb Filter with Reduced Operational Requirements

Patent: 5,835,390 →

Application: 08/580,272 →

Analog-To-Digital Converter Employing Dc Offset Cancellation After Modulation and Before Digital Processing

Patent: 5,721,547 →

Application: 08/582,644 →

An Apparatus and Method for Switching Capacitors Within a Switched Capacitor Circuit at Times Selected to Avoid Data Dependent Loading Upon Reference Voltage Supplies

Patent: 5,790,064 →

Application: 08/630,390 →

Combination Shared Capacitor Integrator and Digital-to-Analog Converter Circuit with Data Dependency Cancellation

Patent: 5,729,232 →

Application: 08/630,436 →

A Phase-Locked Loop Which Can Automatically Adjust to and Lock Upon a Variable Input Frequency

Patent: 6,049,254 →

Application: 08/951,650 →

Phase-Locked Loop with Protected Output During Instances When the Phase-Locked Loop Is Unlocked

Patent: 6,005,904 →

Application: 08/951,796 →

Apparatus and Method for Clocking Digital and Analog Circuits on a Common Substrate to Enhance Digital Operation and Reduce Analog Sampling Error

Patent: 6,057,791 →

Application: 09/025,157 →

Communication System Employing a Network of Power Managed Transceivers That Can Generate a Clocking Signal or Enable Data Bypass of a Digital System Associated with Each Transceiver

Patent: 6,763,060 →

Application: 09/253,469 →

Encoder Within a Communication System That Avoids Encoded Dc Accumulation and Can Use Coding Violations to Synchronize a Decoder and Detect Transmission Errors

Patent: 6,437,710 →

Application: 09/710,220 →

Communication System and Methodology for Addressing and Sending Data of Dissimilar Type and Size Across Channels Formed Within a Locally Synchronized Bus

Patent: 6,922,747 →

Application: 10/157,097 →

Publication: US 2003/0225953

Communication System and Methodology for Sending a Designator for at Least One of a Set of Time-Division Multiplexed Channels Forwarded Across a Locally Synchronized Bus

Patent: 6,874,048 →

Application: 10/157,673 →

Publication: US 2003/0225951

Communication System and Method for Sending Isochronous Streaming Data Within a Frame Segment Using a Signaling Byte

Patent: 7,327,742 →

Application: 10/180,696 →

Publication: US 2004/0001495

Communication System and Method for Sending Asynchronous Data and/or Isochronous Streaming Data Across a Synchronous Network Within a Frame Segment Using a Coding Violation to Signify at Least the Beginning of a Data Transfer

Patent: 7,283,564 →

Application: 10/180,729 →

Publication: US 2004/0003108

Communication System and Method for Sending Isochronous Streaming Data Across a Synchronous Network Within a Frame Segment Using a Coding Violation to Signify Invalid or Empty Bytes Within the Frame Segment

Patent: 7,164,691 →

Application: 10/180,741 →

Publication: US 2004/0003109

Related Assignments (25)

Other recorded transfers of the patents in this record — the chain of ownership.

Assignment of Assignor's Interest Jun 7, 1995

From: FUJIMORI, ICHIRO

To: ASAHI KASEI MICROSYSTEMS CO., LTD.; OASIS DESIGN INC.

Reel/Frame 007543/0399 →

Assignment of Assignor's Interest Nov 13, 1995

From: KNAPP, DAVID J.; HO, HORACE C.

To: OASIS DESIGN, INC.