IP Library › Assignment 017537/0307
Patent Assignment
Reel/Frame 017537/0307

Assignment of Assignor's Interest

Recorded: 2006-04-27 Pages: 20
Assignor
LEGERITY, INC.
Executed: 2006-03-24
Assignee
SAXON IP ASSETS LLC
4509 FREIDRICH LANE, BUILDING 2, AUSTIN, TEXAS, 78744
Covered Properties (211)
Method and Apparatus for Sequencing Addresses of a Fast Fourier Transform Array
Patent: 4,393,457 →
Application: 06/247,676 →
Zero-Crossing Interpolator to Reduce Isochronous Distortion in a Digital Fsk Modem
Patent: 4,412,339 →
Application: 06/305,015 →
Fluorine Plasma Oxidation of Residual Sulfur Species
Patent: 4,501,061 →
Application: 06/499,747 →
High Speed Referenceless Bipolar Logic Gate with Minimun Input Current
Patent: 4,538,075 →
Application: 06/529,917 →
Method for Interconnecting Metallic Layers
Patent: 4,451,326 →
Application: 06/529,920 →
Emitter Coupled Logic Having Enhanced Speed Characteristic for Turn - Off
Patent: 4,617,478 →
Application: 06/530,176 →
Dynamic Ecl Circuit Adapted to Drive Loads Having Significant Capacitance
Patent: 4,539,493 →
Application: 06/550,528 →
Ecl Logic Circuit with a Bias Circuit for Dynamically Switchable Low Drop Current Source
Patent: 4,547,881 →
Application: 06/550,529 →
Ecl Gate with Switched Load Current Source
Patent: 4,551,638 →
Application: 06/562,802 →
Output Voltage Driver with Transient Active Pull-Down
Patent: 4,577,125 →
Application: 06/564,812 →
Process for Forming Slots Having Near Vertical Sidewalls at Their Upper Extremities
Patent: 4,533,430 →
Application: 06/567,971 →
Process for Forming Slots of Different Types in Self-Aligned Relationship Using a Latent Image Mask
Patent: 4,579,812 →
Application: 06/576,658 →
Current Source Arrangement for Three-Level Emitter-Coupled Logic and Four-Level Current Mode Logic
Patent: 4,737,663 →
Application: 06/585,315 →
Forming a Conductive, Protective Layer for Multilayer Metallization
Patent: 4,580,332 →
Application: 06/593,335 →
Temperature Tracking and Supply Voltage Independent Line Driver for Ecl Circuits
Patent: 4,559,458 →
Application: 06/597,618 →
Phase Detector
Patent: 4,628,461 →
Application: 06/605,320 →
Switched Capacitor Coupled Line Receiver Circuit
Patent: 4,651,134 →
Application: 06/681,447 →
Controllable Effective Resistance and Phase Lock Loop with Controllabe Filter
Patent: 4,608,543 →
Application: 06/682,384 →
Low Order Charge-Pump Filter
Patent: 4,668,918 →
Application: 06/697,374 →
Phase Detector and Phase-Locked Loop Apparatus
Patent: 4,686,481 →
Application: 06/697,545 →
Multilevel Differential Ecl/Cml Gate Circuit
Patent: 4,670,673 →
Application: 06/702,962 →
Method of Making an Isolation Slot for Integrated Circuit Structure
Patent: 4,621,414 →
Application: 06/707,728 →
Method of Making an Intergrated Circuit Structure with Self-Aligned Extrinsic Base from Emitter
Patent: 4,641,416 →
Application: 06/707,730 →
Method of Fabricating Integrated Circuit Structure Having Cmos and Bipolar Devices
Patent: 4,604,790 →
Application: 06/718,393 →
Method for Planarizing an Isolation Slot in an Integrated Circuit Structure
Patent: 4,626,317 →
Application: 06/719,185 →
Method of Making Integrated Bipolar Semiconductor Device by First Forming Junction Isolation Regions and Recessed Oxide Isolation Regions Without Birds Beak
Patent: 4,622,738 →
Application: 06/720,824 →
Integrated Circuit Structure Having Conductive, Protective Layer for Multilayer Metallization to Permit Reworking
Patent: 4,672,420 →
Application: 06/722,957 →
Temperature Compensation for Ecl Circuits
Patent: 4,745,304 →
Application: 06/730,709 →
Fast Bipolar Transistor for Integrated Circuit Structure and Method for Forming Same
Patent: 4,682,409 →
Application: 06/747,517 →
Serial Port Synchronizer
Patent: 4,737,722 →
Application: 06/759,623 →
Programmable Data-Routing Multiplexer
Patent: 4,736,362 →
Application: 06/759,624 →
Process for Smoothing a Non-Planar Surface
Patent: 4,655,874 →
Application: 06/759,625 →
Merged Pmos/Bipolar Logic Circuits
Patent: 4,612,458 →
Application: 06/770,817 →
Anti-Corrosion Treatment for Patterning of Metallic Layers
Patent: 4,668,335 →
Application: 06/771,386 →
Bipolar and Mos Devices Fabricated on Same Integrated Circuit Substrate
Patent: 4,922,318 →
Application: 06/777,149 →
Method of Making a Planar Structure Containing Mos and Bipolar Transistors
Patent: 4,707,456 →
Application: 06/777,153 →
Integrated Circuit Fabrication Process for Forming a Bipolar Transistor Having Extrinsic Base Regions
Patent: 4,669,179 →
Application: 06/794,357 →
Ringing Application Circuit
Patent: 4,652,701 →
Application: 06/795,367 →
Ttl Compatible Merged Bipolar/Cmos Output Buffer Circuits
Patent: 4,678,940 →
Application: 06/817,228 →
High-Speed Full Differential Amplifier with Common Mode Rejection
Patent: 4,667,165 →
Application: 06/831,012 →
High Speed Operational Amplifier
Patent: 4,668,919 →
Application: 06/831,020 →
Signal Processor Memory Management Unit with Indirect Addressing Using Selectable Offsets & Modulo Values for Indexed Address Calculations
Patent: 4,935,867 →
Application: 06/836,025 →
Reduced Power/Temperature Controlled Ttl Tri- State Buffer Utilizing Three Phase Splitter Transistors
Patent: 4,672,242 →
Application: 06/836,786 →
Pointer Inplemented Fifo Controller for Converting a Standard Ram into a Simulated Dual Fifo by Controlling the Ram,S Address Inputs.
Patent: 4,949,301 →
Application: 06/836,936 →
Fracturable X-Y Storage Array Using a Ram Cell with Bidirectional Shift
Patent: 4,813,015 →
Application: 06/838,993 →
Dynamic Ecl Line Driver Circuit
Patent: 4,687,953 →
Application: 06/853,504 →
Mos Transistor Construction with Self Aligned Silicided Contacts to Gate, Source, and Drain Regions
Patent: 4,929,992 →
Application: 06/869,759 →
Time-Slot Assigner Multiplexer
Patent: 4,771,418 →
Application: 06/891,438 →
Word-Sliced Signal Processor
Patent: 4,800,517 →
Application: 06/891,713 →
Vertical Slot Bottom Bipolar Transistor Structure
Patent: 4,749,661 →
Application: 06/897,686 →
Data Assembly Apparatus and Method
Patent: 4,809,166 →
Application: 06/900,949 →
Ic Input Circuitry Programmable for Realizing Multiple Functions from a Single Input
Patent: 4,721,868 →
Application: 06/910,595 →
Integrated Circuit Structure with Active Elements of Bipolar Transistor Formed in Slots
Patent: 4,733,287 →
Application: 06/922,625 →
Dual-Port Timing Controller
Patent: 4,809,269 →
Application: 07/035,687 →
Packet-At-A-Time Reporting in a Data Link Controller
Patent: 4,852,088 →
Application: 07/035,817 →
Phase Detector and Phase-Locked Loop Apparatus
Patent: 4,766,397 →
Application: 07/047,077 →
Communication Filter
Patent: 4,835,776 →
Application: 07/073,532 →
Defect Skipping Mechanism for Disk Drives
Patent: 4,811,124 →
Application: 07/077,252 →
Propagating Fifo Storage Device
Patent: 4,805,139 →
Application: 07/111,476 →
Method of Making Bipolar and Mos Devices on Same Integrated Circuit Substrate
Patent: 4,808,548 →
Application: 07/123,823 →
Fddi Bit Error Rate Tester
Patent: 5,023,872 →
Application: 07/173,325 →
Integrated Scr Current Sourcing Sinking Device
Patent: 4,891,683 →
Application: 07/193,232 →
Asynchronous Interrupt Status Bit Circuit
Patent: 4,862,409 →
Application: 07/205,636 →
Method for Transfer of Data Between a Media Access Controller and Buffer Memory in a Token Ring Network
Patent: 4,914,652 →
Application: 07/226,610 →
A Method of Generating Updated Transversal Filter Coefficients
Patent: 4,931,973 →
Application: 07/245,617 →
Modular Test Structure for Single Chip Digital Exchange Controller
Patent: 4,926,363 →
Application: 07/251,309 →
System for Detecting and Correcting Errors Generated by Arithmetic Logic Units
Patent: 4,994,993 →
Application: 07/262,658 →
Reliable Recovery of Data in Encoder/Decoder
Patent: 4,890,304 →
Application: 07/268,396 →
A Ram Cell Having Means for Controlling a Bidirectional Shift
Patent: 4,864,544 →
Application: 07/272,563 →
Methods and Apparatus for Performing Restricted Token Operations on an Fddi Network
Patent: 4,979,167 →
Application: 07/278,724 →
Method and Apparatus for Configuring Data Paths Within a Supernet Station
Patent: 4,951,280 →
Application: 07/281,991 →
Data Link Controler with Flexible Multiplexer
Patent: 5,048,012 →
Application: 07/311,411 →
Asynchronous Interrupt Status Bit Circuit
Patent: 4,897,810 →
Application: 07/318,098 →
Method and Apparatus for Testing a Binary Counter
Patent: 4,979,193 →
Application: 07/343,215 →
Programmable Threshold Detection Logic for a Digital Storage Buffer
Patent: 4,969,164 →
Application: 07/343,622 →
Bit Residue Correction in a Dlc Receiver
Patent: 5,138,641 →
Application: 07/343,810 →
High Speed Static Ram Sensing System
Patent: 5,068,830 →
Application: 07/349,564 →
System and Method for Providing Digital Filter Coefficients
Patent: 5,058,047 →
Application: 07/359,022 →
Data Protocol Controller
Patent: 4,907,225 →
Application: 07/368,083 →
High Speed Digital to Analog to Digital Communication System
Patent: 5,115,450 →
Application: 07/376,882 →
Dynamic Pla Circuit with No "Virtual Grounds"
Patent: 4,950,928 →
Application: 07/407,000 →
Apparatus Adaptable for Use in Effecting Communications Between an Analog Device and a Digital Device
Patent: 4,994,801 →
Application: 07/428,614 →
Apparatus Having a Modular Decimation Architecture
Patent: 4,999,626 →
Application: 07/428,628 →
Apparatus Having Shared Modular Architecture for Decimation and Interpolation
Patent: 4,996,528 →
Application: 07/434,271 →
Programmable Logic Array Apparatus
Patent: 5,021,690 →
Application: 07/434,797 →
Enhanced Universal Asynchronous Receiver-Transmitter
Patent: 4,949,333 →
Application: 07/443,088 →
Capacitively Coupled Read-Only Memory
Patent: 5,020,025 →
Application: 07/462,625 →
Cmos Precharge and Equalization Circuit
Patent: 5,036,492 →
Application: 07/480,401 →
Ecl Output Buffer Circuit with Imrpoved Compensation
Patent: 5,072,136 →
Application: 07/509,916 →
An Address Modulo Adjust Unit for a Memory Management Unit for Monolithic Digital Signal Processor
Patent: 5,440,705 →
Application: 07/516,984 →
Fifo Information Storage Apparatus Including Status and Logic Modules for Each Cell
Patent: 5,095,462 →
Application: 07/528,864 →
Method of and System for Transferring Multiple Priority Queues into Multiple Logical Fifos Using a Single Physical Fifo
Patent: 5,043,981 →
Application: 07/529,366 →
Error Detection and Correction Circuit
Patent: 5,251,219 →
Application: 07/579,721 →
System and Method for Processor Bus Use
Patent: 5,247,621 →
Application: 07/588,194 →
Microprocessor to External Device Serial Bus Communication System
Patent: 5,298,921 →
Application: 07/589,380 →
Method for Operating an Apparatus for Facilitating Communications
Patent: 5,021,783 →
Application: 07/589,402 →
Counter Cell Including a Latch Circuit, Control Circuit and a Pull-Up Circuit
Patent: 5,175,753 →
Application: 07/678,510 →
Processing System Including Memory Selection of Multiple Memories and Method in an Interrupt Environment
Patent: 5,293,591 →
Application: 07/712,944 →
Power Reduction Design for Ecl Outputs That Is Independent of Random Termination Voltage
Patent: 5,122,686 →
Application: 07/732,383 →
System for Converting a Floating Point Signed Magnitude Binary Number to a Two's Complement Binary Number
Patent: 5,272,654 →
Application: 07/766,814 →
Digital Multiplication and Accumulation System
Patent: 5,420,815 →
Application: 07/783,837 →
Apparatus for Generating a Sinusoidal Output Signal
Patent: 5,189,381 →
Application: 07/785,497 →
Method and Apparatus for Determining the Product of Two Numbers
Patent: 5,136,537 →
Application: 07/794,995 →
Apparatus for Adaptively Tuning to a Received Periodic Signal
Patent: 5,339,251 →
Application: 07/796,318 →
Comparator Circuit
Patent: 5,287,015 →
Application: 07/824,029 →
Ram Based Fifo Memory Half-Full Detection Apparatus and Method
Patent: 5,490,257 →
Application: 07/840,024 →
Apparatus and Method for Discriminating and Suppressing Noise Within an Incoming Signal
Patent: 5,369,791 →
Application: 07/887,076 →
Apparatus and Method for Attenuation a Received Signal in Response to Presence of Noise
Patent: 5,299,233 →
Application: 07/887,469 →
Architecture for Covariance Matrix Generation
Patent: 5,299,144 →
Application: 07/900,000 →
Digital Signal Processing Apparatus with Sequencer Designating Program Routines
Patent: 5,379,388 →
Application: 07/910,699 →
External Memory Access Control for a Processing System
Patent: 5,408,639 →
Application: 07/917,489 →
Apparatus for Providing Power to Selected Portions of a Multiplying Device
Patent: 5,200,912 →
Application: 07/924,346 →
Frequency Controlled Recursive Oscillator Having Sinusoidal Output
Patent: 5,204,642 →
Application: 07/939,119 →
System for Interfacing Wafer Sort Prober Apparatus and Packaged Ic Handler Apparatus to a Common Test Computer
Patent: 5,489,852 →
Application: 07/973,089 →
Fast Counter with Uniform Delay Structures
Patent: 5,287,394 →
Application: 08/034,955 →
Method and Apparatus for Multiplying a Plurality of Numbers
Patent: 5,291,430 →
Application: 08/042,825 →
Arithmetic Logic Unit
Patent: 5,282,153 →
Application: 08/044,891 →
Digital Signal Processing Apparatus
Patent: 5,347,480 →
Application: 08/053,959 →
Apparatus for Adaptively Tuning to a Received Periodic Signal
Patent: 5,343,414 →
Application: 08/054,408 →
Coherent Multiplexer Controller
Patent: 5,481,215 →
Application: 08/094,610 →
Interrupt Vector Method and Apparatus
Patent: 5,473,763 →
Application: 08/100,152 →
Method and Apparatus for Combining a Flash Analog to Digital Converter with Digital to Analog Functions
Patent: 5,345,234 →
Application: 08/114,335 →
Power-Efficient External Memory Access Control Using External Memory Enable Time Durations Independent of External Memory Accessing Rate
Patent: 5,481,690 →
Application: 08/140,820 →
Apparatus and Method for Discriminating Signal Noise from Saturated Signals and from High Amplitude Signals
Patent: 5,507,037 →
Application: 08/152,316 →
Variable Thermal Sensor
Patent: 5,422,832 →
Application: 08/172,038 →
Clock Generator Capable of Shut-Down Mode and Clock Generation Method
Patent: 5,502,689 →
Application: 08/201,077 →
Method and Apparatus for Multiplying a Plurality of Numbers
Patent: 5,452,242 →
Application: 08/204,004 →
Synchronous Dual Word Decoding Using Pla
Patent: 5,446,401 →
Application: 08/214,529 →
Apparatus and Method for Synthesizing a Sinusoidal Signal
Patent: 5,615,139 →
Application: 08/217,309 →
Method and Apparatus for Multiplying a Plurality of N Numbers
Patent: 5,424,970 →
Application: 08/257,197 →
Up/Down Counter Apparatus
Patent: 5,428,654 →
Application: 08/257,543 →
Apparatus and Method for Discriminating and Suppressing Noise Within an Incoming Signal
Patent: 5,459,750 →
Application: 08/280,297 →
A System for Receiving a Data Stream of Serialized Data
Patent: 5,845,085 →
Application: 08/316,803 →
Counter Cell and Counter Circuit
Patent: 5,495,513 →
Application: 08/343,990 →
Interrupt Mask Disable Circuit and Method
Patent: 5,530,597 →
Application: 08/346,834 →
Improved Error Detection and Correction Circuit
Patent: 5,751,744 →
Application: 08/379,107 →
Charge Dissipation in Capacitively Loaded Ports
Patent: 5,546,039 →
Application: 08/423,059 →
Interrupt Vector Method and Apparatus for Loading a Slot Memory Address Counter
Patent: 5,678,048 →
Application: 08/433,757 →
Interrupt Vector Method and Apparatus
Patent: 5,557,764 →
Application: 08/433,758 →
Multiple Address Security Architecture
Patent: 5,640,393 →
Application: 08/460,319 →
Write Cache for Servicing Write Requests Within a Predetermined Address Range
Patent: 5,761,709 →
Application: 08/464,352 →
System and Method for Compiling and Executing Sequences of Macro and Micro Instructions
Patent: 5,740,420 →
Application: 08/548,661 →
System for Reconfiguring the Width of an X-Y Ram
Patent: 5,737,767 →
Application: 08/555,081 →
System and Method for Performing Predictive Scaling in Computing Lpc Speech Coding Coefficients
Patent: 5,673,361 →
Application: 08/556,262 →
Microprocessor Configured to Switch Instruction Sets Upon Detection of a Plurality of Consecutive Instructions
Patent: 5,930,490 →
Application: 08/582,124 →
Instruction Translation Unit Configured to Translate from a First Instruction Set to a Second Instruction Set
Patent: 5,826,089 →
Application: 08/583,154 →
Microprocessor Configured to Dynamically Connect Processing Elements According to Data Dependencies
Patent: 5,790,880 →
Application: 08/583,157 →
Time Dependent Rerouting of Instructions in Plurality of Reservation Stations of a Superscalar Microprocessor
Patent: 5,649,138 →
Application: 08/583,193 →
Microprocessor Configured to Detect Memory Operations Having Data Addresses Indicative of a Boundary Between Instructions Sets
Patent: 5,930,489 →
Application: 08/599,617 →
Digital to Analog Converter and Dynamic Current Mirror Structure to Simplify on-Chip Wave Shaping
Patent: 5,739,780 →
Application: 08/599,653 →
System and Method for Error Correction in a Correlation-Based Pitch Estimator
Patent: 5,864,795 →
Application: 08/603,366 →
Microprocessor Configured to Detect a Group of Instructions and to Perform a Specific Function Upon Detection
Patent: 5,829,031 →
Application: 08/605,869 →
Computer System Configured to Translate a Computer Program into a Second Computer Program Prior to Executing the Computer Program
Patent: 5,819,067 →
Application: 08/605,875 →
Digital Phase Lock Loop and System for Digital Clock Recovery
Patent: 5,812,619 →
Application: 08/608,165 →
Data Cache and Method Using a Stack Memory for Storing Stack Data Separate from Cache Line Storage
Patent: 5,930,820 →
Application: 08/617,412 →
Vocoder System and Method for Performing Pitch Estimation Using an Adaptive Correlation Sample Window
Patent: 5,696,873 →
Application: 08/620,758 →
A MICROP0ROCESSOR Configured to Route Instructions of a Second Instruction Set to a Second Execute Unit in Response to an Escape Instruction
Patent: 5,968,162 →
Application: 08/626,473 →
System and Method for Performing Pitch Estimation and Error Checking on Low Estimated Pitch Values in a Correlation Based Pitch Estimator
Patent: 5,774,836 →
Application: 08/626,728 →
Serial Display Drive for Electronic Systems
Patent: 5,874,930 →
Application: 08/628,271 →
Execute Unit Configured to Selectably Interpret an Operand as Multiple Operands or as a Single Operand
Patent: 6,092,094 →
Application: 08/633,352 →
Data Cache Configured to Store Data in a Use-Once Manner
Patent: 5,829,028 →
Application: 08/643,343 →
Dispersed Impulse Generator System and Method for Efficiently Computing an Excitation Signal in a Speech Production Model
Patent: 5,778,337 →
Application: 08/643,522 →
Processor Having a Bus Interconnect Which Is Dynamically Reconfigurable in Response to an Instruction Field
Patent: 5,771,362 →
Application: 08/649,810 →
Microprocessor Configured to Translate Instructions from One Instruction Set to Another, and to Store the Translated Instructions
Patent: 6,711,667 →
Application: 08/672,475 →
Servo System Controlled by Master and Second Processors Through Memory Being Accessed for Read and Write by Processors in Separate Portions Respectively
Patent: 5,630,165 →
Application: 08/673,317 →
Device and Method for Interprocessor Communication Using Mailboxes Owned by Processor Devices
Patent: 5,608,873 →
Application: 08/675,217 →
Apparatus Having Signal Processors for Providing Respective Signals to Master Processor to Notify That Newly Written Data Can Be Obtained from One or More Memories
Patent: 5,771,394 →
Application: 08/675,304 →
Inertial Delay Circuit for Eliminating Glitches on a Signal Line
Patent: 5,760,612 →
Application: 08/696,087 →
Positive Edge Triggered Flip Flop
Patent: 5,781,053 →
Application: 08/701,016 →
System and Method for Generating Re-Configurable Band Limited Noise Using Modulation
Patent: 5,797,120 →
Application: 08/707,700 →
Station Management Circuit
Patent: 5,946,462 →
Application: 08/727,029 →
System and Method for Isolation of Varying-Power Backed Memory Controller Inputs
Patent: 6,144,219 →
Application: 08/785,896 →
Power on/Off Control Circuit and Method
Patent: 6,104,217 →
Application: 08/822,975 →
Communication Within an Integrated Circuit by Data Serialization Through a Metal Plane
Patent: 5,886,539 →
Application: 08/835,935 →
Servo Loop Control Apparatus Having Master Processor to Control the Apparatus and Second Processor Dedicated to Specific Preprogrammed Servo Loop Control Tasks
Patent: 5,771,393 →
Application: 08/842,323 →
Apparatus and Method for Analyzing Speech Signals to Determine Parameters Expressive of Characteristics of the Speech Signals
Patent: 5,745,648 →
Application: 08/851,411 →
Adaptive Speech Recognition with Selective Input Data to a Speech Classifier
Patent: 6,044,343 →
Application: 08/883,978 →
Speech Recognition System Having a Quantizer Using a Single Robust Codebook Designed at Multiple Signal to Noise Ratios
Patent: 6,003,003 →
Application: 08/883,979 →
A Distance Measure in a Speech Recognition System for Speech Recognition Using Frequency Shifting Factors to Compensate for Input Signal Frequency Shifts
Patent: 6,032,116 →
Application: 08/883,980 →
Digitally Controlled Transmission Line Equalizer
Patent: 6,240,131 →
Application: 08/884,932 →
Arrangement for Storing Program Instructions and Data in a Memory Device and Method Therefor
Patent: 6,154,820 →
Application: 08/886,190 →
Digital to Analog Converter and Dynamic Current Mirror Structure to Simplify on-Chip Wave Shaping
Patent: 5,861,830 →
Application: 08/900,954 →
Method of and Apparatus for Dynamically Controlling Operating Characteristics O F a Microphone
Patent: 5,949,892 →
Application: 08/901,679 →
Line Spectral Frequencies and Energy Features in a Robust Signal Recognition System
Patent: 6,009,391 →
Application: 08/907,145 →
Circuit and Method for Protocol Header Decoding and Packet Routing
Patent: 6,122,278 →
Application: 08/908,415 →
Modulated Bus Computer System Having Filters with Different Frequency Coverages for Devices on the Bus
Patent: 6,014,719 →
Application: 08/914,611 →
Apparatus for and Method of Communicating Data Among Devices Interconnected on a Bus
Patent: 6,111,885 →
Application: 08/915,563 →
Apparatus for and Method of Communicating Among Devices Interconnected on a Bus
Patent: 5,936,960 →
Application: 08/915,642 →
Apparatus for and Method of Communicating Among Devices Interconnected on a Bus
Patent: 6,111,886 →
Application: 08/915,688 →
Apparatus for and Method of Communicating Data Among Devices Interconnected on a Bus by Using a Signalling Channel to Set Up Communications
Patent: 6,073,197 →
Application: 08/915,764 →
Apparatus for and Method of Communicating Among Devices Interconnected on a Bus
Patent: 6,104,722 →
Application: 08/916,031 →
System and Method for Determining a First Formant Analysis Filter and Prefiltering a Speech Signal for Improved Pitch Estimation
Patent: 6,047,254 →
Application: 08/957,099 →
First Formant Location Determination and Removal from Speech Correlation Information for Pitch Detection
Patent: 6,026,357 →
Application: 08/957,595 →
Split Matrix Quantization with Split Vector Quantization Error Compensation and Selective Enhanced Processing for Robust Speech Recognition
Patent: 6,067,515 →
Application: 08/957,903 →
Squelch Circuit and Methodology for a Multi-Level Quantizer
Patent: 6,101,376 →
Application: 08/964,857 →
Central Processing Unit Including Apx and Dsp Cores Which Receives and Processes Apx and Dsp Instructions
Patent: 6,032,247 →
Application: 08/969,865 →
Doppler Shift Detector
Patent: 5,900,834 →
Application: 08/992,626 →
Self-Clocked Logic Circuit and Methodology
Patent: 6,064,232 →
Application: 08/992,634 →
System for Recovery of Digital Data from Amplitude and Phase Modulated Line Signals Using Delay Lines
Patent: 6,178,208 →
Application: 08/992,813 →
System for Providing Amplitude and Phase Modulation of Line Signals Using Delay Lines
Patent: 6,160,856 →
Application: 08/992,816 →
Programmable Delay Line
Patent: 6,046,620 →
Application: 08/992,962 →
Analog Delay Line Implemented with a Digital Delay Line Technique
Patent: 6,218,880 →
Application: 08/993,519 →
Power Amplifier Arrangement and Method for Data Signal Interface
Patent: 5,898,342 →
Application: 09/009,389 →
Mlse Implementation Using a General Purpose Dsp and Shared Hardware for a Gsm Application
Patent: 6,195,782 →
Application: 09/086,098 →
Method and Apparatus for Product Development
Patent: 6,412,055 →
Application: 09/106,880 →
Publication: US 2001/0011339
Matrix Quantization with Vector Quantization Error Compensation and Neural Network Postprocessing for Robust Speech Recognition
Patent: 6,347,297 →
Application: 09/166,640 →
Quantization Using Frequency and Mean Compensated Frequency Input Data for Robust Speech Recognition
Patent: 6,219,642 →
Application: 09/166,648 →
Method and Apparatus for Detecting a Sinusoidal Signal
Patent: 6,252,428 →
Application: 09/286,991 →
Method and Apparatus for Detecting a Sinusoidal Signal Using a Counter and Queue
Patent: 6,246,267 →
Application: 09/286,998 →
Dual-Mode Ac/Dc Electrical Receptacle
Patent: 6,160,728 →
Application: 09/320,523 →
Heat Sink
Patent: 6,208,517 →
Application: 09/393,419 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Sep 24, 1981
From: ALFKE, PETER H.; STAUFFER, MICHAEL K.
To: ADVANCED MICRO DEVICES, INC., A CORP. OF DE
Reel/Frame 003931/0060 →
Assignment of Assignors Interest. Oct 5, 1981
From: NEW, BERNARD J.
To: ADVANCED MICRO DEVICES, INC., A CORP. OF DE
Reel/Frame 003914/0465 →
Security Interest Nov 14, 2000
From: LEGERITY, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 011601/0539 →
Assignment of Assignor's Interest Apr 23, 2001
From: ADVANCED MICRO DEVICES, INC.
To: LEGERITY, INC.
Reel/Frame 011700/0686 →
Assignment of Assignor's Interest Jun 25, 2002
From: LUCENT TECHNOLOGIES INC.
To: AGERE SYSTEMS GUARDIAN CORP.
Reel/Frame 013036/0219 →
Security Agreement Oct 21, 2002
From: LEGERITY, INC.; LEGERITY HOLDINGS, INC.; LEGERITY INTERNATIONAL, INC.
To: MORGAN STANLEY & CO. INCORPORATED, AS FACILITY COLLATERAL AGENT
Reel/Frame 013372/0063 →
Release of Security Interest Aug 7, 2007
From: MORGAN STANLEY SENIOR FUNDING INC., AS ADMINISTRATIVE AGENT, SUCCESSOR TO MORGAN STANLEY & CO. INCORPORATED
To: LEGERITY, INC.
Reel/Frame 019690/0647 →
Release of Security Interest Aug 7, 2007
From: MORGAN STANLEY SENIOR FUNDING INC., AS ADMINISTRATIVE AGENT, SUCCESSOR TO MORGAN STANLEY & CO. INCORPORATED, AS FACILITY COLLATERAL AGENT
To: LEGERITY, INC.; LEGERITY HOLDINGS, INC.; LEGERITY INTERNATIONAL, INC.
Reel/Frame 019699/0854 →
Assignment of Assignor's Interest Nov 20, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020134/0701 →
Assignment of Assignor's Interest Nov 20, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020134/0690 →
Assignment of Assignor's Interest Nov 26, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020143/0473 →
Assignment of Assignor's Interest Nov 26, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020143/0554 →
Assignment of Assignor's Interest Nov 26, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020143/0561 →
Assignment of Assignor's Interest Nov 26, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020143/0570 →
Assignment of Assignor's Interest Nov 26, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020143/0550 →
Assignment of Assignor's Interest Nov 27, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020166/0067 →
Assignment of Assignor's Interest Nov 27, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020156/0023 →
Assignment of Assignor's Interest Nov 27, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020156/0033 →
Assignment of Assignor's Interest Nov 27, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020156/0053 →
Assignment of Assignor's Interest Nov 27, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020156/0070 →
Assignment of Assignor's Interest Nov 27, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020156/0254 →
Assignment of Assignor's Interest Nov 27, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020156/0258 →
Assignment of Assignor's Interest Nov 27, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020166/0063 →
Assignment of Assignor's Interest Dec 5, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020196/0328 →
Assignment of Assignor's Interest Dec 5, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020196/0332 →