IP Library › Assignment 011601/0539
Patent Assignment
Reel/Frame 011601/0539

Security Interest

Recorded: 2000-11-14 Pages: 51
Assignor
LEGERITY, INC.
Executed: 2000-08-04
Assignee
MORGAN STANLEY & CO. INCORPORATED
1585 BROADWAY, NEW YORK, NEW YORK, 10036
Covered Properties (564)
Monolithic Digital-to-Analog Converter
Patent: 4,292,625 →
Application: 06/057,046 →
Circuit with Feedback for Controlling the Impedance Thereof
Patent: 4,359,609 →
Application: 06/161,489 →
Current Controlled Battery Feed Circuit
Patent: 4,315,207 →
Application: 06/161,490 →
Method and Apparatus for Sequencing Addresses of a Fast Fourier Transform Array
Patent: 4,393,457 →
Application: 06/247,676 →
Fluorine Plasma Oxidation of Residual Sulfur Species
Patent: 4,501,061 →
Application: 06/499,747 →
High Speed Referenceless Bipolar Logic Gate with Minimun Input Current
Patent: 4,538,075 →
Application: 06/529,917 →
Method for Interconnecting Metallic Layers
Patent: 4,451,326 →
Application: 06/529,920 →
Emitter Coupled Logic Having Enhanced Speed Characteristic for Turn - Off
Patent: 4,617,478 →
Application: 06/530,176 →
Dynamic Ecl Circuit Adapted to Drive Loads Having Significant Capacitance
Patent: 4,539,493 →
Application: 06/550,528 →
Ecl Logic Circuit with a Bias Circuit for Dynamically Switchable Low Drop Current Source
Patent: 4,547,881 →
Application: 06/550,529 →
Ecl Gate with Switched Load Current Source
Patent: 4,551,638 →
Application: 06/562,802 →
Output Voltage Driver with Transient Active Pull-Down
Patent: 4,577,125 →
Application: 06/564,812 →
Process for Forming Slots Having Near Vertical Sidewalls at Their Upper Extremities
Patent: 4,533,430 →
Application: 06/567,971 →
Process for Forming Slots of Different Types in Self-Aligned Relationship Using a Latent Image Mask
Patent: 4,579,812 →
Application: 06/576,658 →
Current Source Arrangement for Three-Level Emitter-Coupled Logic and Four-Level Current Mode Logic
Patent: 4,737,663 →
Application: 06/585,315 →
Forming a Conductive, Protective Layer for Multilayer Metallization
Patent: 4,580,332 →
Application: 06/593,335 →
Temperature Tracking and Supply Voltage Independent Line Driver for Ecl Circuits
Patent: 4,559,458 →
Application: 06/597,618 →
Phase Detector
Patent: 4,628,461 →
Application: 06/605,320 →
Controllable Effective Resistance and Phase Lock Loop with Controllabe Filter
Patent: 4,608,543 →
Application: 06/682,384 →
Low Order Charge-Pump Filter
Patent: 4,668,918 →
Application: 06/697,374 →
Phase Detector and Phase-Locked Loop Apparatus
Patent: 4,686,481 →
Application: 06/697,545 →
Multilevel Differential Ecl/Cml Gate Circuit
Patent: 4,670,673 →
Application: 06/702,962 →
Method of Making an Isolation Slot for Integrated Circuit Structure
Patent: 4,621,414 →
Application: 06/707,728 →
Method of Making an Intergrated Circuit Structure with Self-Aligned Extrinsic Base from Emitter
Patent: 4,641,416 →
Application: 06/707,730 →
Method of Fabricating Integrated Circuit Structure Having Cmos and Bipolar Devices
Patent: 4,604,790 →
Application: 06/718,393 →
Method for Planarizing an Isolation Slot in an Integrated Circuit Structure
Patent: 4,626,317 →
Application: 06/719,185 →
Method of Making Integrated Bipolar Semiconductor Device by First Forming Junction Isolation Regions and Recessed Oxide Isolation Regions Without Birds Beak
Patent: 4,622,738 →
Application: 06/720,824 →
Temperature Compensation for Ecl Circuits
Patent: 4,745,304 →
Application: 06/730,709 →
Fast Bipolar Transistor for Integrated Circuit Structure and Method for Forming Same
Patent: 4,682,409 →
Application: 06/747,517 →
Method for Filling a Trench in an Integrated Circuit Structure Without Producing Voids
Patent: 4,714,520 →
Application: 06/759,621 →
Serial Port Synchronizer
Patent: 4,737,722 →
Application: 06/759,623 →
Programmable Data-Routing Multiplexer
Patent: 4,736,362 →
Application: 06/759,624 →
Process for Smoothing a Non-Planar Surface
Patent: 4,655,874 →
Application: 06/759,625 →
Merged Pmos/Bipolar Logic Circuits
Patent: 4,612,458 →
Application: 06/770,817 →
Anti-Corrosion Treatment for Patterning of Metallic Layers
Patent: 4,668,335 →
Application: 06/771,386 →
Bipolar and Mos Devices Fabricated on Same Integrated Circuit Substrate
Patent: 4,922,318 →
Application: 06/777,149 →
Method of Making a Planar Structure Containing Mos and Bipolar Transistors
Patent: 4,707,456 →
Application: 06/777,153 →
Integrated Circuit Fabrication Process for Forming a Bipolar Transistor Having Extrinsic Base Regions
Patent: 4,669,179 →
Application: 06/794,357 →
Ttl Compatible Merged Bipolar/Cmos Output Buffer Circuits
Patent: 4,678,940 →
Application: 06/817,228 →
High-Speed Full Differential Amplifier with Common Mode Rejection
Patent: 4,667,165 →
Application: 06/831,012 →
High Speed Operational Amplifier
Patent: 4,668,919 →
Application: 06/831,020 →
Signal Processor Memory Management Unit with Indirect Addressing Using Selectable Offsets & Modulo Values for Indexed Address Calculations
Patent: 4,935,867 →
Application: 06/836,025 →
Reduced Power/Temperature Controlled Ttl Tri- State Buffer Utilizing Three Phase Splitter Transistors
Patent: 4,672,242 →
Application: 06/836,786 →
Pointer Inplemented Fifo Controller for Converting a Standard Ram into a Simulated Dual Fifo by Controlling the Ram,S Address Inputs.
Patent: 4,949,301 →
Application: 06/836,936 →
Fracturable X-Y Storage Array Using a Ram Cell with Bidirectional Shift
Patent: 4,813,015 →
Application: 06/838,993 →
Dynamic Ecl Line Driver Circuit
Patent: 4,687,953 →
Application: 06/853,504 →
Fire Retardant Treatments for Polyester/Cotton Fabrics
Application: 06/870,892 →
Image Forming Apparatus
Application: 06/873,535 →
Aircraft Battery Assembly
Patent: 4,762,978 →
Application: 06/888,766 →
Time-Slot Assigner Multiplexer
Patent: 4,771,418 →
Application: 06/891,438 →
Vertical Slot Bottom Bipolar Transistor Structure
Patent: 4,749,661 →
Application: 06/897,686 →
Data Assembly Apparatus and Method
Patent: 4,809,166 →
Application: 06/900,949 →
Ic Input Circuitry Programmable for Realizing Multiple Functions from a Single Input
Patent: 4,721,868 →
Application: 06/910,595 →
Integrated Circuit Structure with Active Elements of Bipolar Transistor Formed in Slots
Patent: 4,733,287 →
Application: 06/922,625 →
Dual-Port Timing Controller
Patent: 4,809,269 →
Application: 07/035,687 →
Packet-At-A-Time Reporting in a Data Link Controller
Patent: 4,852,088 →
Application: 07/035,817 →
Phase Detector and Phase-Locked Loop Apparatus
Patent: 4,766,397 →
Application: 07/047,077 →
Protection System for Cmos Integrated Circuits
Patent: 4,819,047 →
Application: 07/050,979 →
Communication Filter
Patent: 4,835,776 →
Application: 07/073,532 →
Defect Skipping Mechanism for Disk Drives
Patent: 4,811,124 →
Application: 07/077,252 →
Digital Tone Detection and Generation
Patent: 4,839,842 →
Application: 07/077,268 →
Weak/Strong Bus Driver
Patent: 4,941,126 →
Application: 07/077,349 →
Anti-Ulcer Composition
Patent: 4,806,548 →
Application: 07/081,496 →
Master/Slave Synchronizer
Patent: 4,860,285 →
Application: 07/111,475 →
Propagating Fifo Storage Device
Patent: 4,805,139 →
Application: 07/111,476 →
Digital-To-Analog Converter with No Offset-Induced Errors
Patent: 4,843,394 →
Application: 07/146,459 →
Pseudo-Ternary Code Transmitter
Patent: 4,829,541 →
Application: 07/146,988 →
Fddi Bit Error Rate Tester
Patent: 5,023,872 →
Application: 07/173,325 →
Integrated Scr Current Sourcing Sinking Device
Patent: 4,891,683 →
Application: 07/193,232 →
Asynchronous Interrupt Status Bit Circuit
Patent: 4,862,409 →
Application: 07/205,636 →
Ttl Output Driver Gate Configuration
Patent: 4,918,332 →
Application: 07/206,761 →
Digital Tone Generation Based on Difference Equations
Patent: 5,121,350 →
Application: 07/211,835 →
Electrostatic Discharge Protection Circuitry for Any Two External Pins of an I.C. Package
Patent: 4,870,530 →
Application: 07/212,282 →
Fully Differential Non-Linear Amplifier
Patent: 4,849,708 →
Application: 07/213,546 →
Method for Transfer of Data Between a Media Access Controller and Buffer Memory in a Token Ring Network
Patent: 4,914,652 →
Application: 07/226,610 →
Modular Test Structure for Single Chip Digital Exchange Controller
Patent: 4,926,363 →
Application: 07/251,309 →
System for Detecting and Correcting Errors Generated by Arithmetic Logic Units
Patent: 4,994,993 →
Application: 07/262,658 →
Reliable Recovery of Data in Encoder/Decoder
Patent: 4,890,304 →
Application: 07/268,396 →
A Ram Cell Having Means for Controlling a Bidirectional Shift
Patent: 4,864,544 →
Application: 07/272,563 →
Methods and Apparatus for Performing Restricted Token Operations on an Fddi Network
Patent: 4,979,167 →
Application: 07/278,724 →
Method and Apparatus for Configuring Data Paths Within a Supernet Station
Patent: 4,951,280 →
Application: 07/281,991 →
Time Continuous, Differential Analog-to-Digital Converter
Patent: 4,887,085 →
Application: 07/286,198 →
A Voltage Source Amplifier for Use in a Pseudoternary Code Transmitter
Patent: 4,899,114 →
Application: 07/299,908 →
Data Link Controler with Flexible Multiplexer
Patent: 5,048,012 →
Application: 07/311,411 →
Apparatus and Method for Proper Byte Alignment in an Encoder/Decoder
Patent: 5,063,575 →
Application: 07/339,722 →
Method and Apparatus for Testing a Binary Counter
Patent: 4,979,193 →
Application: 07/343,215 →
Programmable Threshold Detection Logic for a Digital Storage Buffer
Patent: 4,969,164 →
Application: 07/343,622 →
Bit Residue Correction in a Dlc Receiver
Patent: 5,138,641 →
Application: 07/343,810 →
High Speed Static Ram Sensing System
Patent: 5,068,830 →
Application: 07/349,564 →
Segmented Waveform Generator
Patent: 4,962,344 →
Application: 07/356,794 →
System and Method for Providing Digital Filter Coefficients
Patent: 5,058,047 →
Application: 07/359,022 →
Data Protocol Controller
Patent: 4,907,225 →
Application: 07/368,083 →
Shielded Transistor Device
Patent: 4,994,891 →
Application: 07/369,572 →
High Speed Digital to Analog to Digital Communication System
Patent: 5,115,450 →
Application: 07/376,882 →
Operational Amplifier Having Selectable Inputs
Patent: 4,972,157 →
Application: 07/383,914 →
Trimming Circuit
Patent: 5,047,664 →
Application: 07/383,918 →
Adaptive Echo-Canceller with Double-Talker Detection
Patent: 5,014,263 →
Application: 07/401,497 →
Dynamic Pla Circuit with No "Virtual Grounds"
Patent: 4,950,928 →
Application: 07/407,000 →
Switchable Dac with Current Surge Protection
Patent: 5,023,614 →
Application: 07/407,447 →
Apparatus Adaptable for Use in Effecting Communications Between an Analog Device and a Digital Device
Patent: 4,994,801 →
Application: 07/428,614 →
Apparatus Having a Modular Decimation Architecture
Patent: 4,999,626 →
Application: 07/428,628 →
Apparatus Having Shared Architecture for Analog-to-Digital and for Digital-to-Analog Signal Conversion
Patent: 5,003,309 →
Application: 07/428,629 →
Apparatus Having Modular Interpolation Architecture
Patent: 5,043,932 →
Application: 07/429,207 →
Apparatus Having Shared Modular Architecture for Decimation and Interpolation
Patent: 4,996,528 →
Application: 07/434,271 →
Programmable Logic Array Apparatus
Patent: 5,021,690 →
Application: 07/434,797 →
Enhanced Universal Asynchronous Receiver-Transmitter
Patent: 4,949,333 →
Application: 07/443,088 →
Capacitively Coupled Read-Only Memory
Patent: 5,020,025 →
Application: 07/462,625 →
Cmos Clamp Circuits
Patent: 5,027,008 →
Application: 07/480,400 →
Cmos Precharge and Equalization Circuit
Patent: 5,036,492 →
Application: 07/480,401 →
Ecl Output Buffer Circuit with Imrpoved Compensation
Patent: 5,072,136 →
Application: 07/509,916 →
An Address Modulo Adjust Unit for a Memory Management Unit for Monolithic Digital Signal Processor
Patent: 5,440,705 →
Application: 07/516,984 →
Fifo Information Storage Apparatus Including Status and Logic Modules for Each Cell
Patent: 5,095,462 →
Application: 07/528,864 →
Fddi Controller Having Flexible Buffer Management
Patent: 5,247,626 →
Application: 07/529,364 →
Method of and System for Transferring Multiple Priority Queues into Multiple Logical Fifos Using a Single Physical Fifo
Patent: 5,043,981 →
Application: 07/529,366 →
Integrated Comparator Circuit
Patent: 5,136,183 →
Application: 07/544,737 →
Communications Processor for Voice Band Telecommunications
Patent: 6,230,255 →
Application: 07/548,709 →
Ram Buffer Controller for Providing Simulated First-in-First-Out (Fifo) Buffers in a Random Access Memory
Patent: 5,133,062 →
Application: 07/566,743 →
Improved Synchronizing Circuit of Two Clock Signals
Patent: 5,086,236 →
Application: 07/572,716 →
Error Detection and Correction Circuit
Patent: 5,251,219 →
Application: 07/579,721 →
System and Method for Processor Bus Use
Patent: 5,247,621 →
Application: 07/588,194 →
Keypad Status Reporting System
Patent: 5,220,601 →
Application: 07/589,065 →
Keypad Monitor with Keypad Activity-Based Activation
Patent: 5,235,635 →
Application: 07/589,090 →
Apparatus for Discriminating Information Signals from Noise Signals in a Communication Signal
Patent: 5,134,658 →
Application: 07/589,315 →
Fully-Integrated Telephone Unit
Patent: 5,199,064 →
Application: 07/589,327 →
Echo Supression with Both Digital and Analog Variable Attenuators
Patent: 5,075,687 →
Application: 07/589,330 →
Microprocessor to External Device Serial Bus Communication System
Patent: 5,298,921 →
Application: 07/589,380 →
Method for Operating an Apparatus for Facilitating Communications
Patent: 5,021,783 →
Application: 07/589,402 →
Positive Edge Triggered Synchronized Pulse Generator
Patent: 5,087,835 →
Application: 07/666,101 →
Counter Cell Including a Latch Circuit, Control Circuit and a Pull-Up Circuit
Patent: 5,175,753 →
Application: 07/678,510 →
Switchable Dac with Current Surge Protection
Patent: 5,184,129 →
Application: 07/712,146 →
Processing System Including Memory Selection of Multiple Memories and Method in an Interrupt Environment
Patent: 5,293,591 →
Application: 07/712,944 →
Power Reduction Design for Ecl Outputs That Is Independent of Random Termination Voltage
Patent: 5,122,686 →
Application: 07/732,383 →
System and Method for Producing Baseband Analog Modulation Signals
Patent: 5,237,324 →
Application: 07/754,644 →
System for Converting a Floating Point Signed Magnitude Binary Number to a Two's Complement Binary Number
Patent: 5,272,654 →
Application: 07/766,814 →
Method of and System for Implementing Multiple Levels of Asynchronous Priority in Fddi Networks
Patent: 5,119,374 →
Application: 07/769,755 →
Transceiver for Full Duplex Signalling on a Fiber Optic Cable
Patent: 5,317,441 →
Application: 07/779,829 →
Digital Multiplication and Accumulation System
Patent: 5,420,815 →
Application: 07/783,837 →
Apparatus for Generating a Sinusoidal Output Signal
Patent: 5,189,381 →
Application: 07/785,497 →
Method and Apparatus for Determining the Product of Two Numbers
Patent: 5,136,537 →
Application: 07/794,995 →
Apparatus for Adaptively Tuning to a Received Periodic Signal
Patent: 5,339,251 →
Application: 07/796,318 →
Encryption System
Patent: 5,199,074 →
Application: 07/817,150 →
Comparator Circuit
Patent: 5,287,015 →
Application: 07/824,029 →
Ram Based Fifo Memory Half-Full Detection Apparatus and Method
Patent: 5,490,257 →
Application: 07/840,024 →
Apparatus for Controlling a Current Supply Device
Patent: 5,249,226 →
Application: 07/844,482 →
Method for Fabricating Diodes for Electrostatic Discharge Protection and Voltage References
Patent: 5,272,097 →
Application: 07/864,933 →
Improved Two-Stage-Analog-to-Digital Converter
Patent: 5,296,858 →
Application: 07/882,666 →
Apparatus and Method for Discriminating and Suppressing Noise Within an Incoming Signal
Patent: 5,369,791 →
Application: 07/887,076 →
Apparatus and Method for Attenuation a Received Signal in Response to Presence of Noise
Patent: 5,299,233 →
Application: 07/887,469 →
Network Chip with Auto Sensing and Reconfiguration
Patent: 5,469,437 →
Application: 07/897,731 →
Architecture for Covariance Matrix Generation
Patent: 5,299,144 →
Application: 07/900,000 →
Digital Signal Processing Apparatus with Sequencer Designating Program Routines
Patent: 5,379,388 →
Application: 07/910,699 →
External Memory Access Control for a Processing System
Patent: 5,408,639 →
Application: 07/917,489 →
General I/O Port Interrupt Mechanism
Patent: 5,448,743 →
Application: 07/917,497 →
Signal Averager
Patent: 5,420,904 →
Application: 07/918,621 →
Serial Interface Module and Method in Which the Clock Is Only Activated to Send a Predetermined Number of Data Bits
Patent: 5,404,459 →
Application: 07/918,624 →
Integrated Circuit and Cordless Telephone Using the Integrated Circuit
Patent: 5,555,287 →
Application: 07/918,627 →
Apparatus for Providing Power to Selected Portions of a Multiplying Device
Patent: 5,200,912 →
Application: 07/924,346 →
Frequency Controlled Recursive Oscillator Having Sinusoidal Output
Patent: 5,204,642 →
Application: 07/939,119 →
Programmable Keypad Monitor
Patent: 5,266,950 →
Application: 07/942,359 →
Voltage Comparator with Hysteresis
Patent: 5,446,396 →
Application: 07/964,781 →
Decorrelation Controller for an Adaptive Echo Cancellor
Patent: 5,526,347 →
Application: 07/970,088 →
System for Interfacing Wafer Sort Prober Apparatus and Packaged Ic Handler Apparatus to a Common Test Computer
Patent: 5,489,852 →
Application: 07/973,089 →
Subscriber Line Interface Circuit with Reduced on-Chip Power Dissipation
Patent: 5,428,682 →
Application: 08/031,785 →
Fast Counter with Uniform Delay Structures
Patent: 5,287,394 →
Application: 08/034,955 →
Method and Apparatus for Multiplying a Plurality of Numbers
Patent: 5,291,430 →
Application: 08/042,825 →
Arithmetic Logic Unit
Patent: 5,282,153 →
Application: 08/044,891 →
Digital Signal Processing Apparatus
Patent: 5,347,480 →
Application: 08/053,959 →
Apparatus for Adaptively Tuning to a Received Periodic Signal
Patent: 5,343,414 →
Application: 08/054,408 →
Low Voltage Digital-to-Analog Converter with Imporved Accuracy
Patent: 5,400,027 →
Application: 08/074,914 →
Operational Amplifier for Low Supply Voltage Applications
Patent: 5,457,426 →
Application: 08/085,898 →
Apparatus and Method for Asynchronous Successive Approximation
Patent: 5,515,050 →
Application: 08/088,007 →
Diodes for Electrostatic Discharge Protection and Voltage References
Patent: 5,426,322 →
Application: 08/093,074 →
Coherent Multiplexer Controller
Patent: 5,481,215 →
Application: 08/094,610 →
Keypad Scanner
Patent: 5,621,402 →
Application: 08/095,923 →
Interrupt Vector Method and Apparatus
Patent: 5,473,763 →
Application: 08/100,152 →
Method and Apparatus for Combining a Flash Analog to Digital Converter with Digital to Analog Functions
Patent: 5,345,234 →
Application: 08/114,335 →
Analog-To-Digital Converter with Multi-Level Dither Current Input
Patent: 5,416,481 →
Application: 08/126,545 →
Method and Apparatus for Protecting Cordless Telephone Account Authentication Information
Patent: 5,384,847 →
Application: 08/130,636 →
Gradual on Output Buffer Circuit Including a Reverse Turn-Off Apparatus
Patent: 5,424,653 →
Application: 08/132,548 →
Method and Apparatus for High Speed Analog to Digital Conversion Using Multiplexed Flash Sections
Patent: 5,450,085 →
Application: 08/139,007 →
Power-Efficient External Memory Access Control Using External Memory Enable Time Durations Independent of External Memory Accessing Rate
Patent: 5,481,690 →
Application: 08/140,820 →
Low Distortion Operational Amplifier
Patent: 5,410,273 →
Application: 08/146,543 →
Fuse Trimming in Plastic Package Devices
Patent: 5,384,727 →
Application: 08/149,191 →
Apparatus and Method for Discriminating Signal Noise from Saturated Signals and from High Amplitude Signals
Patent: 5,507,037 →
Application: 08/152,316 →
Low Distortion Output Stage
Patent: 5,442,309 →
Application: 08/168,103 →
Low Noise Apparatus for Receiving an Input Current and Producing an Output Current Which Mirrors the Input Current
Patent: 5,444,363 →
Application: 08/168,628 →
Variable Thermal Sensor
Patent: 5,422,832 →
Application: 08/172,038 →
Metering Signal Level Control Circuit
Patent: 5,452,345 →
Application: 08/184,564 →
Single Chip Telephone Answering Machine, Telephone, Speakerphone, and Adsi Controller
Patent: 5,483,577 →
Application: 08/185,697 →
Method and Apparatus for Improved Link Establishment and Monitoring in a Communications System
Patent: 5,697,062 →
Application: 08/191,818 →
Input/Output Data Port with a Parallel and Serial Interface
Patent: 5,596,724 →
Application: 08/191,948 →
Dual-Mode Baseband Controller for Radio-Frequency Interfaces Relating to Digital Cordless Telephones
Patent: 5,638,405 →
Application: 08/192,046 →
Clock Generator Capable of Shut-Down Mode and Clock Generation Method
Patent: 5,502,689 →
Application: 08/201,077 →
Method and Apparatus for Multiplying a Plurality of Numbers
Patent: 5,452,242 →
Application: 08/204,004 →
Synchronous Dual Word Decoding Using Pla
Patent: 5,446,401 →
Application: 08/214,529 →
Apparatus and Method for Synthesizing a Sinusoidal Signal
Patent: 5,615,139 →
Application: 08/217,309 →
Method and Apparatus for Multiplying a Plurality of N Numbers
Patent: 5,424,970 →
Application: 08/257,197 →
Up/Down Counter Apparatus
Patent: 5,428,654 →
Application: 08/257,543 →
Analog Integrated Circuit
Patent: 5,535,281 →
Application: 08/264,883 →
Digital Regenerative Comparator
Patent: 5,514,987 →
Application: 08/265,930 →
Dual Port Memory, Such as Used in Color Lookup Tables for Video Systems
Patent: 5,576,560 →
Application: 08/267,036 →
Apparatus and Method for Discriminating and Suppressing Noise Within an Incoming Signal
Patent: 5,459,750 →
Application: 08/280,297 →
Fuse Trimming in Plastic Package Devices
Patent: 5,412,594 →
Application: 08/287,214 →
A System for Receiving a Data Stream of Serialized Data
Patent: 5,845,085 →
Application: 08/316,803 →
Low Power Emergency Telephone Mode
Patent: 5,495,530 →
Application: 08/320,778 →
Method of Weak Pull-Up Disable and Mechanism Therefor for Use with Microcontroller in Integrated Circuit and Cordless Telephone Using the Integrated Circuit
Patent: 5,731,738 →
Application: 08/332,430 →
Variable Dc Feed Characteristic in a Subscriber Line Interface Circuit
Patent: 5,619,567 →
Application: 08/332,512 →
Digital Noise Shaper Circuit
Patent: 5,598,158 →
Application: 08/333,386 →
Digital Interpolation Circuit for a Digital-to-Analog Converter Circuit
Patent: 5,579,004 →
Application: 08/333,399 →
Digital Decimation and Compensation Filter System
Patent: 5,621,675 →
Application: 08/333,403 →
Hazard-Free Divider Circuit
Patent: 5,528,181 →
Application: 08/333,410 →
A Multi-Stage Digital-to-Analog Conversion Circuit and Method
Patent: 5,585,802 →
Application: 08/333,460 →
Stereo Audio Codec
Patent: 5,589,830 →
Application: 08/333,467 →
Delta-Sigma Adc with Multi-Stagse Decimation Filter and Gain Compensation Filter
Patent: 5,646,621 →
Application: 08/333,535 →
Nonolithic Pc Audio Circuit with Enhanced Digital Wavetable Audio Synthesizer
Patent: 5,659,466 →
Application: 08/333,536 →
Power Control of Circuit Modules Within an Integrated Circuit
Patent: 5,675,808 →
Application: 08/333,537 →
Wavetable Audio Synthesizer with Waveform Volume Control for Eliminating Zipper Noise
Patent: 5,742,695 →
Application: 08/333,562 →
Wavetable Audio Synthesizer with Low Frequency Oscillators for Tremolo and Vibrato Effects
Patent: 5,668,338 →
Application: 08/333,564 →
Digital Wavetable Audio Synthesizer with Delay-Based Effects Processing
Patent: 6,047,073 →
Application: 08/334,462 →
On-Board Ring Signal Generator
Patent: 5,600,713 →
Application: 08/340,386 →
Counter Cell and Counter Circuit
Patent: 5,495,513 →
Application: 08/343,990 →
Interrupt Mask Disable Circuit and Method
Patent: 5,530,597 →
Application: 08/346,834 →
Sigma-Delta Modulator Having Reduced Delay from Input to Output
Patent: 5,648,779 →
Application: 08/352,665 →
Configurable Input Buffer Dependent on Supply Voltage
Patent: 5,477,172 →
Application: 08/354,337 →
Low Voltage Linear Output Buffer Operational Amplifier
Patent: 5,477,190 →
Application: 08/357,953 →
Multiplexed Delta-Sigma Modulator
Patent: 5,627,536 →
Application: 08/364,039 →
Clock Switcher Circuit
Patent: 5,502,409 →
Application: 08/364,436 →
Method for Fabricating Devices for Electrostatic Discharge Protection and Voltage References, and the Resulting Structures
Patent: 5,591,661 →
Application: 08/366,048 →
Apparatus for Detecting and Averaging Data in a Digital Data Stream
Patent: 5,993,057 →
Application: 08/374,191 →
Improved Error Detection and Correction Circuit
Patent: 5,751,744 →
Application: 08/379,107 →
Current Steering Semi-Digital Reconstruction Filter
Patent: 5,625,357 →
Application: 08/389,362 →
Adaptive Echo Cancellation Used with Echo Suppression to Reduce Short and Long Duration Echoes
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Conversion of Compressed Speech Codes Between Attenuated and Unattenuated Formats
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Dc Level Control for an Electronic Telephone Line Card
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Servo System Controlled by Master and Second Processors Through Memory Being Accessed for Read and Write by Processors in Separate Portions Respectively
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Telephone System and Method for Easing Wait Time in Queue
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Metal Programmed Transistor Array
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Charge Dissipation in Capacitively Loaded Ports
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Interrupt Vector Method and Apparatus for Loading a Slot Memory Address Counter
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Integrated Ring Sensor with Fault Detection
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Multiple Address Security Architecture
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Method of Using an Access Point Adjacency Matrix to Establish Handoff in a Wireless Lan
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Keypad Scanner Process and Device and Cordless Telephone Employing the Mechanism
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Motion Controller Architecture
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Variable Frequency Clock Generation Circuit Using Aperiodic Patterns
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Integrated Ring Detection Circuit and Power Cross Detection Circuit with Persistence Timers
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Protection Circuit for Telephone Systems
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Cascode Operational Amplifier with Multiple Input Stage
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Extended Chip Select Reset Apparatus and Method
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Implementation and Method for a Digital Sigma-Delta Modulator
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Analog Voltage Reference Generator System
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Power Supply Dependent Method of Controlling a Charge Pump
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Receiver Quality Measurement System for Use in Digital Cordless Telephones and Like Apparatus
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System and Method for Compiling and Executing Sequences of Macro and Micro Instructions
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Non-Modulo Power of 2 Frequency Divider
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Microprocessor Using an Instruction Field to Define Dsp Instructions
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System for Reconfiguring the Width of an X-Y Ram
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Dsp Architecture for a Fir-Type Filter and Method
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Implementation of a Digital Decimation Filter and Method
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Implementation of a Digital Interpolation Filter and Method
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Narrowband Digital Cordless Telephone with a Logic High Weak Driver and a Logic Low Strong Driver for Keypad Interface
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External Protocol Hooks System and Method
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Microprocessor Configured to Switch Instruction Sets Upon Detection of a Plurality of Consecutive Instructions
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Instruction Translation Unit Configured to Translate from a First Instruction Set to a Second Instruction Set
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Microprocessor Configured to Dynamically Connect Processing Elements According to Data Dependencies
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Time Dependent Rerouting of Instructions in Plurality of Reservation Stations of a Superscalar Microprocessor
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Dtmf Detector System and Method Which Performs Static and Dynamic Thresholding
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Dtmf Detector System and Method Which Performs Improved Twist Computation and Thresholding
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System and Method for Performing Echo Cancellation in a Communications Network Employing a Mixed Mode Lms Adaptive Balance Filter
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Differential Cmos Current Amplifier with Controlled Bandwidth and Common Mode Distortion
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Directional Microphone Utilizing Spaced Apart Omni-Directional Microphones
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Microprocessor Configured to Detect Memory Operations Having Data Addresses Indicative of a Boundary Between Instructions Sets
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Digital to Analog Converter and Dynamic Current Mirror Structure to Simplify on-Chip Wave Shaping
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High Swing, Low Power Output Stage for an Operational Amplifier
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High Swing Low Power General Purpose Operational Amplifier
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Apparatus and Method for Protocol Interface
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Microprocessor Configured to Detect a Group of Instructions and to Perform a Specific Function Upon Detection
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Computer System Configured to Translate a Computer Program into a Second Computer Program Prior to Executing the Computer Program
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Digital Phase Lock Loop and System for Digital Clock Recovery
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High Conversion Gain Cmos Mixer
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Data Cache and Method Using a Stack Memory for Storing Stack Data Separate from Cache Line Storage
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Cpu with Dsp Having Decoder That Detects and Converts Instruction Sequences Intended to Perform Dsp Function into Dsp Function Identifier
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Central Processing Unit Including a Dsp Function Preprocessor Which Scans Instruction Sequences for Dsp Functions
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Cpu with Dsp Function Preprocessor Having Look-Up Table for Translating Instruction Sequences Intended to Perform Dsp Function into Dsp Macros
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Cpu with Dsp Function Preprocessor Having Pattern Recognition Detector That Uses Table for Translating Instruction Sequences Intended to Perform Dsp Function into Dsp Macros
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Vocoder System and Method for Performing Pitch Estimation Using an Adaptive Correlation Sample Window
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Transmit Clock Generation System and Method
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Computer System and Method for Performing Wavetable Music Synthesis Which Stores Wavetable Data in System Memory Employing a High Priority I/O Bus Request Mechanism for Improved Audio Fidelity
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Computer System and Method for Performing Wavetable Music Synthesis Which Stores Wavetable Data in System Memory Which Minimizes Audio Infidelity Due to Wavetable Data Access Latency
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Computer System and Method for Generating Delay-Based Audio Effects in a Wavetable Music Synthesizer Which Stores Wavetable Data in System Memory
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Microprocessor Configured to Detect a Branch to a Dsp Routine and to Direct a Dsp to Execute Said Routine
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Serial Display Drive for Electronic Systems
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Power Cross Detection Using Loop Current and Voltage
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Dsp with Register File and Multi-Function Instruction Sequencer for Vector Processing by Macu
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Data Cache Configured to Store Data in a Use-Once Manner
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Microprocessor Configured to Detect a Dsp Call Instruction and to Direct a Dsp to Execute a Routine Corresponding to the Dsp Call Instruction
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Dispersed Impulse Generator System and Method for Efficiently Computing an Excitation Signal in a Speech Production Model
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Dtmf Detector System and Method Which Performs Frequency Domain Energy Calculations with Improved Performance
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Waveshaper for False Edge Rejection of an Input Signal
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Strobed Comparator for a Large Common Mode Range
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Fourth Order Digital Noise Shaper Circuit
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Microprocessor Configured to Translate Instructions from One Instruction Set to Another, and to Store the Translated Instructions
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Servo System Controlled by Master and Second Processors Through Memory Being Accessed for Read and Write by Processors in Separate Portions Respectively
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Device and Method for Interprocessor Communication Using Mailboxes Owned by Processor Devices
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Programmable Drive Strength Output Buffer with Slew Rate Control
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Stereo Audio Codec
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Inertial Delay Circuit for Eliminating Glitches on a Signal Line
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Combined Analog and Digital Communications Device
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Digital Direct Current Feed Control for a Communication System
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Microprocessor-Controlled Full-Duplex Speakerphone Using Automatic Gain Control
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Apparatus and Method for Receiving a Modulated Radio Frequency Signal by Converting the Radio Frequency Signal to a Very Low Intermediate Frequency Signal
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Positive Edge Triggered Flip Flop
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Communication Channel Coordination System and Method
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Transistor Ratio Controlled Cmos Transmission Line Equalizer
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Parallel Decimator Method and Apparatus
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Method and Apparatus for Entering a Test Mode of an Externally Non-Programmable Device
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System and Method for Performing Automatic Gain Control with Gain Scheduling and Adjustment at Zero Crossings for Reducing Distortion
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Configurable Digital Wireless and Wired Communications System Architecture for Implementing Baseband Functionality
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Station Management Circuit
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High Performance Echo Canceler for High Speed Modem
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Transmit Clock Generation System and Method
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Network Adapter Utilizing an Ethernet Protocol and Utilizing a Digital Subscriber Line Physical Layer Driver for Improved Performance
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Audio Processing Chip with External Serial Port
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System and Method for Performing Software Patches in Embedded Systems
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Communications Device with Improved Ring Signal Detection
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Narrowband Digital Cordless Telephone
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High Speed Analog Flip-Flop with Embedded Logic and Phase-Locked-Loop Circuit Employing the Same
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Ring-Signal Generation in a Slic
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Frequency Ratio Estimation Arrangement and Method Thereof
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Automatically Switching Valve with Remote Signaling
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Dynamic Ram with Two-Transistor Cell
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Multipoint Access Protocol Utilizing a Point-to-Point Methodology
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Power on/Off Control Circuit and Method
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Carrier for an Electronic Identification Device
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Communication Within an Integrated Circuit by Data Serialization Through a Metal Plane
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Pin Count Reduction Through Serialization Techniques
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Secondary Channel for Radio Frequency Communications
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Servo Loop Control Apparatus Having Master Processor to Control the Apparatus and Second Processor Dedicated to Specific Preprogrammed Servo Loop Control Tasks
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Integrated Circuit, Having Microprocessor and Telephony Peripheral Circuitry, Having Capability of Being Placed in Partial Emulation Mode
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System and Method for Implementing a Mute Voice Signal Upon Reception of a Adpcm Zero Nibble in Wireless Communications
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Training Preamble Added to CT2 Muxes in a CT2 Wireless Telecommunications System
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Signal Processing Arrangement Including Variable Length Adaptive Filter and Method Therefor
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Monitoring Line Conditions in the Data Transmission Mode
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A Threshold Voltage Level Generator for Time Division Duplex Communications
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System and Method for Providing Fdd and Tdd Modes of Operation for a Wireless Communications Device
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A Free Channel Selector for Selecting an Optimal Channel
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Wavetable Audio Synthesizer with Waveform Volume Control for Eliminating Zipper Noise
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Data Slicer for Demodulated Binary Fsk Signals in a Time Division Duplex Radio Environment
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Ring Trip Detection in a Communication System
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Silent Polarity Reversal in a Communication System
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Direct Current Feed with Line Status Change Adaptation in a Communication System
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Cable Length Estimation Circuit Using Data Signal Edge Rate Detection and Analog to Digital Conversion
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Electronic Directory System and Method
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Telephony Device with Integrated Messaging
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Phase -Locked Loop Arrangement with Fast Lock Mode
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System and Method for Programmable Telephone Subscriber Line Test
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Telephone Subscriber Line Diagnostics System and Method
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System and Method for Programmable Telephone Subscriber Line Test in Ring Mode
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Storage Device Utilizing a Motion Control Circuit Having an Integrated Digital Signal Processing and Central Processing Unit
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Adaptive Speech Recognition with Selective Input Data to a Speech Classifier
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Speech Recognition System Having a Quantizer Using a Single Robust Codebook Designed at Multiple Signal to Noise Ratios
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A Distance Measure in a Speech Recognition System for Speech Recognition Using Frequency Shifting Factors to Compensate for Input Signal Frequency Shifts
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System and Method for Equalizing Data Buffer Storage and Fetch Rates of Peripheral Devices
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Arrangement for Storing Program Instructions and Data in a Memory Device and Method Therefor
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Wavetable Audio Synthesizer with Multiple Volume Components and Two Modes of Stereo Positioning
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Digital to Analog Converter and Dynamic Current Mirror Structure to Simplify on-Chip Wave Shaping
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Method of and Apparatus for Dynamically Controlling Operating Characteristics O F a Microphone
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Line Spectral Frequencies and Energy Features in a Robust Signal Recognition System
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Semiconductor Memory Device Having Collective Writing Mode for Writing Data on Row Basis
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Method and Apparatus for External Intermediate Data Processing
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Burst Synchronization of Time Division Multiplexed Transceiver Pairs
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Integrated Circuit Reset Incorporating Battery Monitor and Watchdog Timer
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Modulated Bus Computer System Having Filters with Different Frequency Coverages for Devices on the Bus
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Apparatus for and Method of Communicating Data Among Devices Interconnected on a Bus
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Apparatus for and Method of Communicating Among Devices Interconnected on a Bus
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Method of Using an Audio Transmission Signal to Transmit Video Data
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Apparatus for and Method of Communicating Among Devices Interconnected on a Bus
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Method of and Apparatus for Encoding of Output Symbol Size
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Apparatus for and Method of Communicating Data Among Devices Interconnected on a Bus by Using a Signalling Channel to Set Up Communications
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Apparatus for and Method of Communicating Among Devices Interconnected on a Bus
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Low Voltage Fully Differential Operational Amplifier with Improved Common Mode Circuitry
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Electronic System Having a Multistage Low Noise Output Buffer System
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Method of Coding a Number for Storing in a Memory
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Fifo and System Synchronization System and Method
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Monolithic Pc Audio Circuit
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Telephone Calling Party Announcement System and Method
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System and Method for Determining a First Formant Analysis Filter and Prefiltering a Speech Signal for Improved Pitch Estimation
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First Formant Location Determination and Removal from Speech Correlation Information for Pitch Detection
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Matrix Quantization with Vector Quantization Error Compensation for Robust Speech Recognition
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Split Matrix Quantization with Split Vector Quantization Error Compensation and Selective Enhanced Processing for Robust Speech Recognition
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Squelch Circuit and Methodology for a Multi-Level Quantizer
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Iir Filter of Adaptive Balance Circuit for Long Tail Echo Cancellation
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System and Method for Frequency Division Duplex/Time Division Duplex Radio Frequency Communication
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Verification of Pn Synchronization in a Spread-Spectrum Communications Receiver
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System and Method for Identifying and Announcing a Caller and a Callee of an Incoming Telephone Call
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System and Method for Reducing Call Interruptions on a Telephone
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Central Processing Unit Including Apx and Dsp Cores and Including Selectable Apx and Dsp Execution Modes
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Central Processing Unit Including Apx and Dsp Cores Which Receives and Processes Apx and Dsp Instructions
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System and Method for Identifying a Callee of an Incoming Telephone Call
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On-Chip Operating Condition Recorder
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Chip Operating Conditions Compensated Clock Generation
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Signal Detection Circuit Using a Plurality of Delay Stages with Edge Detection Logic
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Parity Checking in a Real-Time Digital Communications System
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Passband Dqpsk Detector for a Digital Communications Receiver
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Communications System with Multiple, Simultaneous Accesses to a Memory
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Configuring a Communications System with a Configurable Data Transfer Architecture
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Programmable Data Flow Processor for Performing Data Transfers
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Doppler Shift Detector
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Self-Clocked Logic Circuit and Methodology
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Analog Delay Line Implemented with a Digital Delay Line Technique
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Silicon Controlled Rectifier with Reduced Substrate Current
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System and Method for Detecting Voice Activity Based on Integrated Absolute Values of the Differentiated Zero Crossing Rate
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System and Method for Detecting Floating Nodes Within a Simulated Integrated Circuit
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Arrangement and Method for Selectable Time/Frequency Division Multiplex Communication
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Apparatus and Method for Decoding Differential Multi-Level Data with Adaptive Threshold Control
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Transcoder-Codec Circuit Arrangement and Method That Supports Voice-Switched Hands-Free Radio Operation
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Wireless Telephony Ring Detection Method for Extended Battery Life
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Method and Apparatus for Modulating Signals
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Communications Device Including an Improved Cpe Alerting Signal (Cas) Detection System
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Method for Compensating Filtering Delays in a Spread-Spectrum Receiver
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Symbol-Quality Evaluation in a Digital Communications Receiver
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System and Method for Automatically Updating a Clock Using Caller Id Information
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Mlse Implementation Using a General Purpose Dsp and Shared Hardware for a Gsm Application
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Mechanism for Changing a Modem's Connection Rate Within a Family of Interoperable Modems
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Method and Apparatus for Power Regulation of Digital Data Transmission
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System Processing Unit Extended with Programmable Logic for Plurality of Functions
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Method and Apparatus for Product Development
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Method and Apparatus for Generating Tones in a Multi-Tone Modem
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Battery Monitor with Software Trim
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Method and Apparatus for Detecting and Measuring Foreign Voltages
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Method and Apparatus for Detecting Message Waiting Signal
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Method and Apparatus for Scaling Modem Transfer Capacity in a Multi-Channel Communications System
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An Integrated Circuit Having a Programmable Input/Output Processor That Is Used for Increasing the Flexibility of Communications
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Frame Synchronization in a Digital Communications System
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Slow Tracking of Pn Synchronization in a Direct-Sequence Spread-Spectrum Digital Communications System
Patent: 6,256,335 →
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Fast Tracking of Pn Synchronization in a Direct-Sequence Spread-Spectrum Digital Communications System
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Rapid Acquisition of Pn Synchronization in a Direct-Sequence Spread-Spectrum Digital Communications System
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Method and Apparatus for Detecting Signal Misalignment
Patent: 6,046,977 →
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Cross-Frame Dual Tone Multifrequency Detector
Patent: 6,587,559 →
Application: 09/159,143 →
Tone Detector with Noise Detection and Dynamic Thresholding for Robust Performance
Patent: 6,711,540 →
Application: 09/160,415 →
Efficient Dynamic Energy Thresholding in Multiple-Tone Multiple Frequency Detectors
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Method and System for Improved Analog Signal Detection
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Method and System for Improved Detection of Analog Signals
Patent: 6,370,555 →
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Enhanced Register Array Accessible by Both a System Microprocessor and a Wavetable Audio Synthesizer
Patent: 6,058,066 →
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Matrix Quantization with Vector Quantization Error Compensation and Neural Network Postprocessing for Robust Speech Recognition
Patent: 6,347,297 →
Application: 09/166,640 →
Quantization Using Frequency and Mean Compensated Frequency Input Data for Robust Speech Recognition
Patent: 6,219,642 →
Application: 09/166,648 →
Timing Recovery for a Pseudo-Random Noise Sequence in a Direct-Sequence Spread-Spectrum Communications System
Patent: 6,002,710 →
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Apparatus and Method for a Phy Transmitter with Programmable Power Mode Control in Cmos
Patent: 6,377,666 →
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Channel Arbitration Between Handset and Base Station in a Cordless Telephone System
Patent: 6,304,756 →
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Digital Cordless Telephony with Pcm Coding
Patent: 6,343,217 →
Application: 09/191,008 →
Signal Detector with Matched Filter Coefficient
Patent: 6,556,674 →
Application: 09/196,258 →
Signal Detector with Duration-Based Frame Width
Patent: 6,763,106 →
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Method and Apparatus for Accessing Variable Sized Blocks of Data
Patent: 6,560,652 →
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Method and Apparatus for Synchronizing Signals
Patent: 6,184,813 →
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Apparatus and Method to Reduce Power Amplifier Noise Generation in a Multiplexed Communication System
Patent: 6,404,824 →
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Apparatus and Method for Broadcast Band Noise Reduction in a Transmitter with a Low If Frequency
Patent: 6,532,270 →
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Compensation of Frequency Pulling in a Time-Division Duplexing Transceiver
Patent: 6,597,754 →
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Signal Detector with Coefficient Swapping Transform Unit
Patent: 6,771,767 →
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Method and Apparatus for Verifying and Correcting Connectivity
Patent: 6,621,831 →
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Signal Detector with Automatic Gain Control
Patent: 6,580,792 →
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Method and System for Providing Security Using Voice Recognition
Patent: 6,263,311 →
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Multi-Tone Transceiver for Multiple Users
Patent: 6,424,674 →
Application: 09/236,122 →
Power-On-Reset Circuit
Patent: 6,198,318 →
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Method for Conserving Power in Transceivers
Patent: 6,611,564 →
Application: 09/243,391 →
Method and Apparatus for Locating a Synchronization Signal
Patent: 6,865,375 →
Application: 09/256,543 →
Transceiver with Variable Width Cyclic Prefix
Patent: 6,535,550 →
Application: 09/257,674 →
Method and Apparatus for Inserting Idle Symbols
Patent: 6,519,280 →
Application: 09/260,251 →
Transceiver with Usage-Based Rate Adaptation
Application: 09/260,252 →
Method and Apparatus for Remotely Resetting a Modem
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Transceiver with Adjustable Coding Gain
Application: 09/260,750 →
Method and Apparatus for Handling Incoming Calls
Patent: 6,763,092 →
Application: 09/263,373 →
Method and Apparatus for Impedance Matching
Patent: 6,728,370 →
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Method and System to Meter and Control Usage of Telephone Systems
Patent: 6,246,756 →
Application: 09/270,707 →
Cordless Infrared Digital Telephone Communication Near-Cd Quality Coded Audio Signals Over Public Switched Telephone Network
Patent: 6,556,965 →
Application: 09/275,173 →
Electronic Book
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Digital Photo Album
Application: 09/282,294 →
Collision Handling Scheme for Discrete Multi-Tone Data Communications Network
Patent: 6,339,599 →
Application: 09/286,987 →
Differential Encoding Arrangement for a Discrete Multi-Tone Transmission System
Patent: 6,434,188 →
Application: 09/286,989 →
Method and Apparatus for Detecting a Sinusoidal Signal
Patent: 6,252,428 →
Application: 09/286,991 →
Method and Apparatus for Achieving Frequency Diversity by Use of Multiple Images
Patent: 6,456,602 →
Application: 09/286,992 →
Method and Apparatus for Frequency Shifting with a Clock Signal
Patent: 6,449,262 →
Application: 09/286,993 →
Collision Detection System for Multiple Stations in Discrete Multi-Tone Data Communications Network
Patent: 6,075,795 →
Application: 09/286,994 →
Timing Recovery Scheme for a Discrete Multitone Transmission System
Patent: 6,442,173 →
Application: 09/286,995 →
Methods and Apparatus for Channel Adaptation in a Dmt Based System
Patent: 6,577,598 →
Application: 09/286,996 →
Adaptive Transmission System in a Network
Patent: 6,590,893 →
Application: 09/286,997 →
Method and Apparatus for Detecting a Sinusoidal Signal Using a Counter and Queue
Patent: 6,246,267 →
Application: 09/286,998 →
Bin-To-Bin Differential Encoding Apparatus and Method for a Discrete Multi-Tone Transmission System
Patent: 6,175,316 →
Application: 09/287,263 →
Keypad Scanning with Few Pins
Patent: 6,424,274 →
Application: 09/290,139 →
Auto-Negotiation for Multiple Ports Using Shared Logic
Patent: 6,115,389 →
Application: 09/291,030 →
Auto-Negotiation Using Negative Link Pulses
Patent: 6,141,350 →
Application: 09/291,036 →
Free Channel Selection Method
Patent: 6,487,418 →
Application: 09/296,969 →
Adaptation Control Algorithm for Echo Cancellation Using Signal-Value Based Analysis
Patent: 6,426,979 →
Application: 09/301,848 →
Dual-Mode Ac/Dc Electrical Receptacle
Patent: 6,160,728 →
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Apparatus for Transmitting and Receiving Signals
Patent: 6,792,286 →
Application: 09/340,576 →
Method and Apparatus for Managing Data Transfer and Acknowledgements
Patent: 6,545,993 →
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Method and Apparatus for Accessing Variable Sized Data with Prioritization
Patent: 6,430,661 →
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Method and Apparatus for Packet Data Transmission and Reception
Patent: 6,625,128 →
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Wavetable Audio Synthesizer with Left Offset, Right Offset and Effects Volume Control
Patent: 7,088,835 →
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Method and Apparatus for Transmitting Data from a Plurality of Users in a Multi-Tone Modem Communications System
Patent: 6,498,807 →
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Method and Apparatus for Allocating Tones to a Plurality of Users in a Multi-Tone Modem Communications System
Patent: 6,501,791 →
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Method and Apparatus for Tracking Signals
Patent: 6,356,765 →
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Method and Apparatus for Frequency Hopping in a Spread Spectrum Digital Cordless Telephone System
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Apparatus and Method for Examining and Standardizing Line Connections
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Apparatus and Method for Facilitating Standardized Testing of Signal Lines
Patent: 6,826,155 →
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Method and Apparatus for Intra-Bundle Signaling
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Method and Apparatus for Encryption and Decryption
Patent: 6,778,670 →
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Method and Apparatus for Optimal Data Transfer in a Multi-Tone Modem Communications System
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Electronic System Having a Multistage Low Noise Output Buffer System
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Computer Peripheral Base Station for a Cordless Telephone
Patent: 6,728,546 →
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Heat Sink
Patent: 6,208,517 →
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Low Noise Logic Gate
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Low-Noise Voltage Controlled Oscillator
Patent: 6,236,280 →
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Low Noise Current Source
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Method and Apparatus for Generating Comfort Noise
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Method and Apparatus for Linking Multiple Modems Through a Single Access Point
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Method and Apparatus for Linking Pots and Dsl Communications with Computer Network Systems
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Method and Apparatus for Prioritizing Interrupts in a Communication System
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Method and Apparatus for Dc Feed Control
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Communication Device with Primitive Synchronization Signal
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Reduced Complexity Fast Transform Engine For Discrete Multi-Tone Transceivers
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Method and Apparatus for Mixing Down and Spectrum Folding Frequency Diverse Modulated Carrier
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Method and Apparatus for Detecting an Activation Tone
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Method for Determining a Decimation Pattern in a Network Communications Receiver
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Method and Apparatus for Sensing Current
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System and method for detecting floating nodes within a simulated integrated circuit
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Method and Apparatus for Switch Hook Detection
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Method of synchronizing independently distributed software and database schema
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Bipolar Junction Transistor Incorporating Integral Field Plate
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Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest May 4, 1998
From: KUBINEC, JAMES J.
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 009145/0787 →
Assignment of Assignor's Interest Oct 23, 1999
From: ADVANCED MICRO DEVICES, INC.
To: VANTIS CORPORATION
Reel/Frame 010340/0329 →
Assignment of Assignor's Interest Oct 26, 1999
From: ADVANCED MICRO DEVICES, INC.
To: VANTIS CORPORATION
Reel/Frame 010310/0899 →
Assignment of Assignor's Interest Apr 23, 2001
From: ADVANCED MICRO DEVICES, INC.
To: LEGERITY, INC.
Reel/Frame 011700/0686 →
Merger Jun 6, 2002
From: VANTIS CORPORATION
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 012937/0738 →
Security Agreement Oct 21, 2002
From: LEGERITY, INC.; LEGERITY HOLDINGS, INC.; LEGERITY INTERNATIONAL, INC.
To: MORGAN STANLEY & CO. INCORPORATED, AS FACILITY COLLATERAL AGENT
Reel/Frame 013372/0063 →
Assignment of Assignor's Interest Apr 27, 2006
From: LEGERITY, INC.
To: SAXON IP ASSETS LLC
Reel/Frame 017537/0307 →
Release of Security Interest Aug 7, 2007
From: MORGAN STANLEY SENIOR FUNDING INC., AS ADMINISTRATIVE AGENT, SUCCESSOR TO MORGAN STANLEY & CO. INCORPORATED
To: LEGERITY, INC.
Reel/Frame 019690/0647 →
Release of Security Interest Aug 7, 2007
From: MORGAN STANLEY SENIOR FUNDING INC., AS ADMINISTRATIVE AGENT, SUCCESSOR TO MORGAN STANLEY & CO. INCORPORATED, AS FACILITY COLLATERAL AGENT
To: LEGERITY, INC.; LEGERITY HOLDINGS, INC.; LEGERITY INTERNATIONAL, INC.
Reel/Frame 019699/0854 →
Assignment of Assignor's Interest Nov 20, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020134/0690 →
Assignment of Assignor's Interest Nov 26, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020143/0554 →
Assignment of Assignor's Interest Nov 26, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020143/0570 →
Assignment of Assignor's Interest Nov 26, 2007
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To: SAXON INNOVATIONS, LLC
Reel/Frame 020143/0473 →
Assignment of Assignor's Interest Nov 26, 2007
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To: SAXON INNOVATIONS, LLC
Reel/Frame 020143/0550 →
Assignment of Assignor's Interest Nov 26, 2007
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Assignment of Assignor's Interest Nov 27, 2007
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To: SAXON INNOVATIONS, LLC
Reel/Frame 020166/0067 →
Assignment of Assignor's Interest Nov 27, 2007
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To: SAXON INNOVATIONS, LLC
Reel/Frame 020156/0023 →
Assignment of Assignor's Interest Nov 27, 2007
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To: SAXON INNOVATIONS, LLC
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Assignment of Assignor's Interest Nov 27, 2007
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Reel/Frame 020156/0053 →
Assignment of Assignor's Interest Nov 27, 2007
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Assignment of Assignor's Interest Nov 27, 2007
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To: SAXON INNOVATIONS, LLC
Reel/Frame 020156/0254 →
Assignment of Assignor's Interest Nov 27, 2007
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To: SAXON INNOVATIONS, LLC
Reel/Frame 020156/0258 →
Assignment of Assignor's Interest Nov 27, 2007
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To: SAXON INNOVATIONS, LLC
Reel/Frame 020166/0063 →
Assignment of Assignor's Interest Dec 5, 2007
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To: SAXON INNOVATIONS, LLC
Reel/Frame 020196/0320 →
Assignment of Assignor's Interest Dec 5, 2007
From: SAXON IP ASSETS, LLC
To: SAXON INNOVATIONS, LLC
Reel/Frame 020196/0312 →