IP Library › Assignment 025446/0029
Patent Assignment
Reel/Frame 025446/0029

Merger

Recorded: 2010-12-07 Pages: 6
Assignor
HUAI TECHNOLOGIES, LLC
Executed: 2010-12-07
Assignee
INTELLECTUAL VENTURES II LLC
2711 CENTERVILLE RD., SUITE 400, WILMINGTON, DELAWARE, 19808
Covered Properties (61)
Single Chip Controller-Memory Device and a Memory Architecture and Methods Suitable for Implementing the Same
Patent: 5,473,573 →
Application: 08/239,608 →
Electronic Memory and Methods for Making and Using the Same
Patent: 5,452,244 →
Application: 08/288,580 →
Dual Bank Memory and Systems Using the Same
Patent: 5,506,810 →
Application: 08/291,093 →
Circuits and Methods for Refreshing a Dual Bank Memory
Patent: 5,442,588 →
Application: 08/291,155 →
Memory Architecture and Devices, Systems and Methods Utilizing the Same
Patent: 5,473,566 →
Application: 08/304,508 →
Circuits, Systems and Methods for Improving Page Accesses and Block Transfers in a Memory System
Patent: 5,500,819 →
Application: 08/315,934 →
Circuits, Systems and Methods for Improving Row Select Speed in a Row Select Memory Device
Patent: 5,701,143 →
Application: 08/381,189 →
Circuits, Systems and Methods for Testing Asic and Ram Memory Devices
Patent: 5,592,077 →
Application: 08/387,218 →
A Multi-Bit Data Storage Location
Patent: 5,567,963 →
Application: 08/410,868 →
Fabricating a Multi-Bit Storage Cell
Patent: 5,529,945 →
Application: 08/410,869 →
Bus Driver/Receiver Circuitry and Systems and Methods Using the Same
Patent: 5,530,392 →
Application: 08/420,138 →
Continuous Page Random Access Memory and Systems and Methods Using the Same
Patent: 5,581,513 →
Application: 08/423,825 →
Circuits, Systems and Methods for Modifying Data Stored in a Memory Using Logic Operations
Patent: 5,732,024 →
Application: 08/424,653 →
High Performance Bus Driving/Receiving Circuits, Systems and Methods
Patent: 5,663,984 →
Application: 08/434,656 →
Circuits, Systems and Methods for Testing Integrated Circuit Devices Including Logic and Memory Circuitry
Patent: 5,535,165 →
Application: 08/497,267 →
Pipeland Address Memories, and Systems and Methods Using the Same
Patent: 5,598,374 →
Application: 08/502,479 →
Low Pin Count-Wide Memory Devices and Systems and Methods Using the Same
Patent: 5,537,353 →
Application: 08/521,867 →
Circuits, Systems and Methods for Controlling Substrate Bias in Integrated Circuits
Patent: 5,612,644 →
Application: 08/521,891 →
Memory Architecture and Devices, Systems and Methods Utilizing the Same
Patent: 5,568,431 →
Application: 08/531,755 →
Circuits, Systems and Methods for Memory Mapping and Display Control Systems Using the Same
Patent: 6,025,840 →
Application: 08/534,279 →
Memory Devices with Selectable Access Type and Methods Using the Same
Patent: 5,654,932 →
Application: 08/538,903 →
Circuits Systems and Methods for Reducing Power Loss During Transfer of Data Across a Conductive Line
Patent: 5,585,744 →
Application: 08/543,210 →
Multiple-Bank Memory Architecture and Systems and Methods Using the Same
Patent: 5,687,132 →
Application: 08/548,752 →
Single Chip Controller-Memory Device and a Memory Architecture and Methods Suitable for Implementing the Same
Patent: 5,583,822 →
Application: 08/551,526 →
Circuits, Systems and Methods for Interfacing Processing Circuitry with a Memory
Patent: 6,108,015 →
Application: 08/552,197 →
A Dual Bank Memory System with Output Multiplexing and Methods Using the Same
Patent: 5,570,320 →
Application: 08/554,297 →
Memory Architecture Using Content Addressable Memory, and Systems and Methods Using the Same
Patent: 6,041,389 →
Application: 08/559,379 →
Multi-Bank Memory System and Method Having Addresses Switched Between the Row and Column Decoders in Different Banks
Patent: 5,761,694 →
Application: 08/565,388 →
Fast Cycle Time-Low Latency Dynamic Random Access Memories and Systems and Methods Using the Same
Patent: 5,636,174 →
Application: 08/584,565 →
Circuits Systems and Methods for Reducing Power Loss During Transfer of Data Across an I/O Bus
Patent: 5,848,101 →
Application: 08/591,864 →
Single Chip Controller-Memory Device with Interbank Cell Replacement Capability and a Memory Architecture and Methods Suitable for Implementing the Same
Patent: 5,701,270 →
Application: 08/595,236 →
Low Pin Count-Wide Memory Devices Using Non-Multiplexed Addressing and Systems and Methods Using the Same
Patent: 5,600,606 →
Application: 08/612,113 →
Systems and Methods for Implementing Inter-Device Cell Replacements
Patent: 5,657,281 →
Application: 08/613,316 →
Circuits Systems and Methods for Reducing Power Loss During Transfer of Data Across a Conductive Line
Patent: 5,644,255 →
Application: 08/620,115 →
A Memory Divice with an Externally Selectable-Width I/O Port and Systems and Methods Using the Same
Patent: 5,906,003 →
Application: 08/633,574 →
Memory System with Multiplexed Input-Output Port and Memory Mapping Capability
Patent: 5,835,965 →
Application: 08/637,073 →
Memory System with Multiplexed Input-Output Port and Systems and Methods Using the Same
Patent: 5,829,016 →
Application: 08/638,953 →
Circuits, Systems and Methods for the High Speed Transfer of Data Across a Conductive Line
Patent: 5,596,291 →
Application: 08/641,708 →
Memory Banks with Pipelining of Address Words During Precharge
Patent: 5,950,219 →
Application: 08/641,887 →
Display Controller with Integrated Half Frame Buffer and Systems and Methods Using the Same
Patent: 5,945,974 →
Application: 08/645,021 →
Memories with Programmable Address Decoding and Systems and Methods Using the Same
Patent: 5,982,696 →
Application: 08/659,664 →
Pipelined Address Memories, and Systems and Methods Using the Same
Patent: 5,745,428 →
Application: 08/664,471 →
Pipelined Address Memories, and Systems and Methods Using the Same
Patent: 5,657,285 →
Application: 08/666,683 →
"Multibank - Multiport Memories and Systems and Methods Using the Same"
Patent: 5,815,456 →
Application: 08/666,814 →
Dual Port Memories and Systems and Methods Using the Same
Patent: 5,844,856 →
Application: 08/666,815 →
Circuits, Systems and Method for Address Mapping
Patent: 6,058,464 →
Application: 08/677,125 →
Circuits, Systems and Methods for Transferring Data Across a Conductive Line
Patent: 5,764,082 →
Application: 08/681,661 →
Circuits, Systems, and Methods for Accounting for Defective Cells in a Memory Device
Patent: 6,513,130 →
Application: 08/726,568 →
Precision Sense Amplifiers and Memories, Systems and Methods Using the Same
Patent: 5,912,853 →
Application: 08/759,760 →
Digital Step Generators and Circuits, Systems and Methods Using the Same
Patent: 5,861,767 →
Application: 08/759,764 →
Circuits, Systems and Methods for Graphics and Video Window/Display Data Block Transfer via Dedicated Memory Control
Patent: 6,157,366 →
Application: 08/862,325 →
Method and Apparatus for Transferring Data in a Dual Port Memory
Patent: 6,510,098 →
Application: 08/864,506 →
Circuits, Systems and Methods for Modifying Data Stored in a Memory Using Logic Operations
Patent: 5,914,900 →
Application: 08/902,674 →
Sensing Circuitry with Boolean Logic
Patent: 5,909,401 →
Application: 08/903,317 →
Circuits, Systems and Methods for Modifying Data Stored in a Memory Using Logic Operations
Patent: 5,910,919 →
Application: 08/903,390 →
Single Chip Controller- Memory Device Including Feature- Selectable Bank I/O and Architecture and Methods Suitable for Implementing the Same
Patent: 6,018,793 →
Application: 08/957,242 →
Circuitry and Methods for Dynamically Sensing of Data in a Static Random Access Memory Cell
Patent: 5,978,293 →
Application: 09/045,757 →
Circuits, Systems and Methods for Memory Mapping and Display Control Systems Using the Same
Patent: 6,118,461 →
Application: 09/066,618 →
Dynamic Random Access Memory with a Normal Precharge Mode and a Priorty Precharge Mode
Patent: 5,920,885 →
Application: 09/088,535 →
Memory with Pipelined Accessed and Priority Precharge
Patent: 6,282,603 →
Application: 09/088,649 →
Memories, Systems and Methods Using Precison Sense Amplifiers
Patent: 5,926,428 →
Application: 09/097,893 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest May 9, 1994
From: RAO, G.R. MOHAN
To: CIRRUS LOGIC, INC.
Reel/Frame 006995/0979 →
Assignment of Assignor's Interest Aug 10, 1994
From: RAO, G.R. MOHAN
To: CIRRUS LOGIC, INC.
Reel/Frame 007106/0329 →
Assignment of Assignor's Interest Aug 16, 1994
From: RUNAS, MICHAEL E.
To: CIRRUS LOGIC, INC.
Reel/Frame 007123/0054 →
Assignment of Assignor's Interest Aug 16, 1994
From: RUNAS, MICHAEL E.
To: CIRRUS LOGIC, INC.
Reel/Frame 007114/0450 →
Assignment of Assignor's Interest Sep 12, 1994
From: RAO, G.R. MOHAN
To: CIRRUS LOGIC, INC.
Reel/Frame 007159/0759 →
Assignment of Assignor's Interest Sep 30, 1994
From: RUNAS, MICHAEL E.
To: CIRRUS LOGIC, INC.
Reel/Frame 007177/0327 →
Assignment of Assignor's Interest Jan 31, 1995
From: RAO, G.R. MOHAN
To: CIRRUS LOGIC, INC.
Reel/Frame 007343/0810 →
Assignment of Assignor's Interest Feb 13, 1995
From: RUNAS, MICHAEL E.; PATEL, KIRIT B.
To: CIRRUS LOGIC, INC.
Reel/Frame 007361/0664 →
Assignment of Assignor's Interest Apr 11, 1995
From: RUNAS, MICHAEL E.; PATEL, KIRIT B.
To: CIRRUS LOGIC, INC.
Reel/Frame 007472/0628 →
Assignment of Assignor's Interest Apr 19, 1995
From: RAO, G.R. MOHAN
To: CIRRUS LOGIC, INC.
Reel/Frame 007450/0730 →
Assignment of Assignor's Interest Apr 19, 1995
From: SHARMA, SUDHIR; RUNAS, MICHAEL E.; NALLY, ROBERT M.
To: CIRRUS LOGIC, INC.
Reel/Frame 007477/0308 →
Assignment of Assignor's Interest May 4, 1995
From: RUNAS, MICHAEL E.
To: CIRRUS LOGIC, INC.
Reel/Frame 007477/0266 →
Assignment of Assignor's Interest Jun 30, 1995
From: DAVIS, PHILLIP D.; SHARMA, SUDHIR; LONG, HAI
To: CIRRUS LOGIC, INC.
Reel/Frame 007571/0925 →
Assignment of Assignor's Interest Jul 14, 1995
From: RAO, G.R. MOHAN
To: CIRRUS LOGIC, INC.
Reel/Frame 007575/0166 →
Assignment of Assignor's Interest Aug 31, 1995
From: RUNAS, MICHAEL E.
To: CIRRUS LOGIC, INC.
Reel/Frame 007625/0634 →
Assignment of Assignor's Interest Aug 31, 1995
From: RAO, G. R. MOHAN; TAYLOR, RONALD T.; SHARMA, SUDHIR
To: CIRRUS LOGIC, INC.
Reel/Frame 007625/0480 →
Assignment of Assignor's Interest Sep 27, 1995
From: TAYLOR, RONALD T.
To: CIRRUS LOGIC, INC.
Reel/Frame 007700/0539 →
Assignment of Assignor's Interest Oct 4, 1995
From: RAO, G. R. MOHAN
To: CIRRUS LOGIC, INC.
Reel/Frame 007695/0390 →
Assignment of Assignor's Interest Oct 13, 1995
From: RUNAS, MICHAEL E.; TAYLOR, RONALD T.
To: CIRRUS LOGIC, INC.
Reel/Frame 007714/0775 →
Assignment of Assignor's Interest Oct 26, 1995
From: MOHAN RAO, G.R.
To: CIRRUS LOGIC, INC.
Reel/Frame 007738/0175 →
Assignment of Assignor's Interest Nov 2, 1995
From: CROSS, RANDOLPH A.
To: CIRRUS LOGIC, INC.
Reel/Frame 007754/0558 →
Security Interest May 14, 1996
From: CIRRUS LOGIC, INC.
To: BANK OF AMERICA NATIONAL TRUST & SAVINGS ASSOCIATION, AS AGENT
Reel/Frame 007986/0917 →
Security Agreement Aug 29, 1996
From: CIRRUS LOGIC, INC.
To: BANK OF AMERICA NATIONAL TRUST & SAVINGS ASSOCIATION AS AGENT
Reel/Frame 008113/0001 →
Deed of Discharge Mar 5, 2003
From: BANK OF AMERICA NATIONAL TRUST SAVINGS ASSOCIATION
To: CIRRUS LOGIC INTERNATIONAL LTD.
Reel/Frame 013782/0435 →
Assignment of Assignor's Interest Aug 2, 2010
From: RAO, G. R. MOHAN
To: CIRRUS LOGIC, INC.
Reel/Frame 024767/0778 →