IP Library › Assignment 033119/0615
Patent Assignment
Reel/Frame 033119/0615

Assignment of Assignor's Interest

Recorded: 2014-06-10 Pages: 14
Assignor
CYPRESS SEMICONDUCTOR CORPORATION
Executed: 2014-06-04
Assignee
RPX CORPORATION
ONE MARKET PLAZA, STEUART TOWER, SUITE 800, SAN FRANCISCO, CALIFORNIA, 94105
Covered Properties (104)
Flash Memory System, and Methods of Constructing and Utilizing Same
Application: 07/970,921 →
Memory Architecture for Burst Mode Access
Patent: 5,453,957 →
Application: 08/123,377 →
Field Shield Isolated Eprom
Patent: 5,510,638 →
Application: 08/234,288 →
Apparatus for a Programmable Cml to Cmos Translator for Power/Speed Adjustment
Application: 08/265,456 →
Output Preconditioning Circuit with an Output Level Latch and a Clamp
Patent: 5,559,465 →
Application: 08/283,223 →
Methods for Maximizing Routability in a Programmable Interconnect Matrix Having Less Than Full Connectability
Application: 08/283,650 →
Apparatus for Smart Power Supply Esd Protection Structure
Patent: 5,625,522 →
Application: 08/297,629 →
Method and Apparatus for a Pulsed Tri-State Phase Detector for Reduced Jitter Clock Recovery
Application: 08/300,644 →
Differential Latch Sense Amplifiers Using Feedback
Patent: 5,504,443 →
Application: 08/301,657 →
Power-On Reset Control Circuit
Patent: 5,737,612 →
Application: 08/316,121 →
Non-Volatile, Static Random Access Memory with Current Limiting
Application: 08/323,814 →
Method and Apparatus for Self-Resetting Logic Circuitry
Application: 08/330,930 →
Method and Apparatus for Cml/Ecl to Cmos/Ttl Translators
Patent: 5,502,405 →
Application: 08/335,908 →
Output Buffer with Variable Output Impedance
Patent: 5,559,447 →
Application: 08/341,371 →
Single Ended Simplex Dual Port Memory Cell
Application: 08/362,814 →
Single Ended Dual Port Memory Cell
Application: 08/363,637 →
Low Jitter Voltage Controlled Oscillator (Vco) Circuit
Patent: 5,581,216 →
Application: 08/377,269 →
Five Transistor Memory Cell with Shared Power Line
Patent: 5,453,950 →
Application: 08/377,952 →
Overvoltage Tolerant Integrated Circuit Output Buffer
Patent: 5,570,043 →
Application: 08/381,125 →
Semiconductor Memory Device Having a Sleep Mode
Patent: 5,563,839 →
Application: 08/413,360 →
Flash Memory System, and Methods of Constructing and Utilizing Same
Patent: 5,644,533 →
Application: 08/427,826 →
Low Power High Voltage Switch with Gate Bias Circuit to Minimize Power Consumption
Patent: 5,604,711 →
Application: 08/446,539 →
High Speed Flash Memory Cell Structure and Method
Patent: 5,648,669 →
Application: 08/452,217 →
Memory Architecture for Burst Mode Access
Patent: 5,831,926 →
Application: 08/473,076 →
Method and Apparatus for Disabling Unused Sense Amplifiers
Patent: 5,565,791 →
Application: 08/498,622 →
Sram with Simplified Architecture for Use with Pipelined Data
Patent: 5,621,695 →
Application: 08/502,974 →
Pseudo-Differential Sense Amplifier
Patent: 5,572,474 →
Application: 08/503,807 →
Apparatus and Method for Improving Common Mode Noise Rejection in Pseudo-Differential Sense Amplifiers
Patent: 5,638,322 →
Application: 08/503,988 →
Buffer with Controlled Hysteresis
Patent: 5,654,645 →
Application: 08/507,849 →
Single Layer Polycrystalline Silicon Split-Gate Eeprom Cell Having a Buried Control Gate
Patent: 5,844,271 →
Application: 08/517,495 →
Five Transistor Memory Cell with Shared Power Line
Application: 08/522,991 →
High-Speed Ratio Cmos Logic Structure with Static and Dynamic Pullups and/or Pulldowns Using Feedback
Patent: 5,654,652 →
Application: 08/534,358 →
Non-Volatile, Static Random Access Memory with Current Limiting
Patent: 5,602,776 →
Application: 08/549,483 →
An Eprom Bit-Line Interface for Implementing Programming, Verification and Testing
Patent: 5,636,161 →
Application: 08/549,919 →
Clock Frequency Synthesis Using Delay-Locked Loop
Application: 08/551,992 →
Method and Apparatus for Performing Collision Detection and Arbitration Within an Expansion Bus Having Multiple Transmission Repeater Units
Patent: 5,740,174 →
Application: 08/552,272 →
Multiple Word Width Memory Array Clocking Scheme
Patent: 5,712,820 →
Application: 08/559,983 →
Clock Synthesizer Dual Function Pin System and Method Therefor
Patent: 5,656,959 →
Application: 08/562,478 →
Apparatus for a Programmable Cml to Cmos Translator for Power/Speed Adjustment
Patent: 5,600,267 →
Application: 08/563,350 →
Improved Testing Method for Fifos
Patent: 5,642,318 →
Application: 08/567,544 →
State Machine Design for Generating Empty and Full Flags in an Asynchronous Fifo
Patent: 5,712,992 →
Application: 08/567,893 →
State Machine Design for Generating Half-Full and Half-Empty Flags in an Asynchronous Fifo
Patent: 5,809,339 →
Application: 08/567,918 →
Phase Locked Loop Having Integration Gain Reduction
Patent: 5,767,713 →
Application: 08/569,682 →
Cross Coupled Differential Oscillator
Application: 08/569,683 →
Read Bitline Writer for Fallthru in Fifo's
Patent: 5,673,234 →
Application: 08/572,181 →
Full and Empty Flag Generator for Synchronous Fifos
Patent: 5,627,797 →
Application: 08/572,623 →
Method and Apparatus for Reducing Skew Among Input Signals Within an Integrated Circuit
Patent: 5,903,174 →
Application: 08/575,554 →
Method and Apparatus for Reducing Skew Between Input Signals and Clock Signals Within an Integrated Circuit
Application: 08/575,555 →
Cache Controller for a Non-Symetric Cache System
Patent: 5,710,905 →
Application: 08/575,985 →
Burst Address Generator Having Two Modes of Operation Employing a Linear/Nonlinear Counter Using Decoded Addresses
Patent: 5,835,970 →
Application: 08/576,505 →
Bubbleback for Fifo's
Application: 08/576,944 →
Data Output Stage Incorporating an Inverting Operational Amplifier
Patent: 5,666,069 →
Application: 08/577,258 →
Circuit Having Plurality of Carry/Sum Adders Having Read Count, Write Count, and Offset Inputs to Generate an Output Flag in Response to Fifo Fullness
Patent: 5,850,568 →
Application: 08/577,712 →
Apparatus and Method for Matching a Clock Delay to a Delay Through a Memory Array
Patent: 5,652,732 →
Application: 08/577,716 →
Two-Stage Differential Sense Amplifier with Positive Feedback in the First and Second Stages
Patent: 5,640,356 →
Application: 08/578,187 →
Programmable Read-Write Word Line Equality Signal Generation for Fifos
Patent: 5,852,748 →
Application: 08/578,209 →
Method and Apparatus for Providing Clock Signals to Macrocells of Logic Devices
Patent: 5,799,176 →
Application: 08/578,478 →
Dummy Cell for Providing a Reference Voltage in a Memory Array
Patent: 5,689,471 →
Application: 08/579,079 →
Bond Optioning Decoding
Application: 08/579,853 →
Apparatus and Method for Generating a Pulse Signal
Application: 08/581,073 →
Method and Apparatus for Providing a Serial Interface Between an Asynchronous Transfer Mode (Atm) Layer and a Physical (Phy) Layer
Patent: 6,452,927 →
Application: 08/581,242 →
Method and Apparatus for Regenerating a Control Signal at an Asynchronous Transfer Mode (Atm) Layer or a Physical (Phy) Layer
Patent: 5,784,370 →
Application: 08/581,267 →
Method and Apparatus for a Pulsed Tri-State Phase Detector for Reduced Jitter Clock Recovery
Patent: 5,640,523 →
Application: 08/598,157 →
Clock Distribution Architecture and Method for High Speed Cplds
Patent: 5,821,794 →
Application: 08/626,043 →
Flash Memory System, and Methods of Constructing and Utilizing Same
Patent: 5,656,837 →
Application: 08/633,857 →
Full and Empty Flag Generator for Synchronous Fifos
Patent: 5,963,056 →
Application: 08/661,436 →
Half-Full Flag Generator for Synchronous Fifos
Patent: 5,844,423 →
Application: 08/666,751 →
Method and Apparatus for Self-Resetting Logic Circuitry
Application: 08/676,888 →
Methods for Maximizing Routability in a Programmable Interconnect Matrix Having Less Than Full Connectability
Patent: 5,848,066 →
Application: 08/705,990 →
Memory Architecture for Burst Mode Access
Patent: 5,787,047 →
Application: 08/745,876 →
Apparatus for Smart Power Supply Esd Protection Structure
Patent: 5,784,242 →
Application: 08/758,336 →
Digital Integration Gain Reduction Method
Patent: 5,818,272 →
Application: 08/760,304 →
Method and Circuit for Reducing Power and/or Current Consumption
Patent: 5,949,261 →
Application: 08/767,767 →
Single Ended Dual Port Memory Cell
Patent: 6,005,795 →
Application: 08/789,299 →
Single Ended Simpler Dual Port Memory Cell
Patent: 6,005,796 →
Application: 08/789,300 →
Method and Apparatus for Self-Resetting Logic Circuitry
Patent: 5,864,251 →
Application: 08/791,002 →
High Speed Flash Memory Cell Structure and Method
Patent: 5,760,438 →
Application: 08/800,656 →
Cross Coupled Differential Oscillator
Patent: 5,896,069 →
Application: 08/815,701 →
Multi-Level Programmable Voltage Control and Output Buffer with Selectable Operating Voltage
Patent: 6,380,762 →
Application: 08/824,634 →
Read Bitline Writer for Fallthru in Fifo's
Patent: 5,862,092 →
Application: 08/852,837 →
Buffer for Memory Modules with Trace Delay Compensation
Patent: 5,867,448 →
Application: 08/873,005 →
Apparatus and Method for Generating a Pulse Signal
Patent: 5,933,032 →
Application: 08/897,375 →
Bond Option Decoding
Patent: 6,515,505 →
Application: 08/902,206 →
State Machine Design for Generating Empty and Full Flags in an Asynchronous Fifo
Patent: 6,016,403 →
Application: 08/911,132 →
Power-On Reset Control Circuit
Patent: 5,809,312 →
Application: 08/920,124 →
Clock Frequency Synthesis Using Delay-Locked Loop
Patent: 5,805,003 →
Application: 08/921,420 →
Bubbleback for Fifos
Patent: 5,880,997 →
Application: 08/939,463 →
Half-Full Flag Generator for Synchronous Fifos
Patent: 5,994,920 →
Application: 08/955,809 →
Method and Apparatus for Reducing Skew Between Input Signals and Clock Signals Within an Integrated Circuit
Patent: 6,043,684 →
Application: 08/960,584 →
Multiple Word Width Memory Array Clocking Scheme
Patent: 5,930,176 →
Application: 09/013,499 →
State Machine Design for Generating Half-Full and Half-Empty Flags in an Asynchronous Fifo
Patent: 5,991,834 →
Application: 09/144,301 →
Methods for Maximizing Routability in a Programmable Interconnect Matrix Having Less Than Full Connectability
Patent: 6,243,664 →
Application: 09/181,084 →
Circuit for Generating Almost Full and Almost Empty Flags in Responce to Sum and Carry Outputs in Asynchronous and Synchronous Fifos
Patent: 6,070,203 →
Application: 09/201,413 →
Method and Apparatus for Reducing Skew Between Input Signals and Clock Signals Within an Integrated Circuit
Patent: 6,411,140 →
Application: 09/307,063 →
Apparatus and Method for Generating a Pulse Signal
Patent: 6,222,393 →
Application: 09/357,474 →
Circuitry, Architecture and Method(S) for Phase Matching and/or Reducing Load Capacitance, Current and/or Power Consumption in an Oscillator
Patent: 6,326,853 →
Application: 09/383,328 →
Method and Circuit for Reducing Power and/or Current Consumption
Application: 09/391,135 →
Publication: US 2002/0000846
Single Ended Simplex Dual Port Memory Cell
Patent: 6,262,912 →
Application: 09/443,062 →
Single Ended Dual Port Memory Cell
Patent: 6,181,595 →
Application: 09/443,126 →
Single Ended Simplex Dual Port Memory Cell
Patent: 6,731,566 →
Application: 09/876,429 →
Circuitry, architecture and method (s) for phase matching and/or reducing load capacitance, current and/or power consumption in an oscillator
Patent: 6,377,128 →
Application: 09/966,603 →
Oscillator Tuning Method
Patent: 6,670,852 →
Application: 09/981,448 →
Multi-Level Programmable Voltage Control and Output Buffer with Selectable Operating Voltage
Patent: 6,664,810 →
Application: 10/043,785 →
Method and Circuit for Reducing Power and/or Current Consumption
Patent: 6,593,785 →
Application: 10/133,851 →
Related Assignments (7)
Other recorded transfers of the patents in this record — the chain of ownership.
Merger May 20, 2014
From: SIMTEK CORPORATION
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 032962/0953 →
Assignment of Assignor's Interest May 20, 2014
From: NORRIS, CHRISTOPHER S.; LACEY, TIMOTHY M.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 032946/0500 →
Assignment of Assignor's Interest May 21, 2014
From: VOSS, PETER H.; LINDEN, JEFFREY L.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 032938/0480 →
Merger May 21, 2014
From: GALVANTECH, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 032938/0224 →
Assignment of Assignor's Interest May 21, 2014
From: SHEEN, BEN YAU; LACEY, TIMOTHY M.; CHEUNG, SAMMY
To: CYPRESS SEMICONDUCTOR
Reel/Frame 032972/0434 →
Security Agreement Mar 9, 2016
From: RPX CORPORATION; RPX CLEARINGHOUSE LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038041/0001 →
Release (Reel 038041 / Frame 0001) Jan 2, 2018
From: JPMORGAN CHASE BANK, N.A.
To: RPX CORPORATION; RPX CLEARINGHOUSE LLC
Reel/Frame 044970/0030 →