Patent Assignment
Reel/Frame 036034/0415
Assignment of Assignor's Interest
Recorded: 2015-06-29
Received: 2015-06-29
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Properties
(46)
Method and a Media Device for Pre-Buffering Media Content Streamed to the Media Device from a Server System
Application:
14/714,154 →
Method and Device for Resumed Playback of Streamed Media
Application:
14/714,161 →
Method and a System for Performing Scrubbing in a Video Stream
Application:
14/714,163 →
Playback of Media Streams in Dependence of a Time of a Day
Application:
14/714,157 →
Alignment System for Planar Charge Trapping Dielectric Memory Cell Lithography
Application:
10/394,565 →
Spin on Polymers for Organic Memory Devices
Application:
10/385,375 →
Method for Fabricating Devices in Core and Periphery Semiconductor Regions Using Dual Spacers
Application:
10/361,455 →
Dc Offset Cancel Circuit
Application:
10/349,107 →
Dc-Dc Converter, Duty-Ratio Setting Circuit and Electric Appliance Using Them
Application:
10/345,352 →
Selective Formation of Top Memory Electrode by Electroless Formation of Conductive Materials
Application:
10/314,837 →
Fabrication of Shallow Trench Isolation Structures with Rounded Corner and Self-Aligned Gate
Application:
10/292,121 →
High Density Floating Gate Flash Memory and Fabrication Processes Therefor
Application:
10/244,229 →
Gain Variable Amplifier
Application:
10/237,720 →
Virtual Ground Silicide Bit Line Process for Floating Gate Flash Memory
Application:
10/238,412 →
Dummy Wordline for Erase and Bitline Leakage
Application:
10/230,729 →
Method of Protecting a Stacked Gate Structure During Fabrication
Application:
10/217,807 →
Current Pulse Receiving Circuit
Application:
10/214,149 →
Generation of Margining Voltage on-Chip During Testing Cam Portion of Flash Memory Device
Application:
10/200,539 →
On-Chip Erase Pulse Counter for Efficient Erase Verify Bist (Built-in-Self-Test) Mode
Application:
10/200,330 →
Shallow Trench Isolation Fill Process
Application:
10/174,550 →
Nitride Barrier Layer for Protection of Ono Structure from Top Oxide Loss in Fabrication of Sonos Flash Memory
Application:
10/158,044 →
Memory Manufacturing Process Using Bitline Rapid Thermal Anneal
Application:
10/151,576 →
Replacing Layers of an Intergate Dielectric Layer with High-K Material for Improved Scalability
Application:
10/145,952 →
Semiconductor Memory with Deuterated Materials
Application:
10/128,771 →
Replacing a First Liner Layer with a Thicker Oxide Layer When Forming a Semiconductor Device
Application:
10/126,841 →
Refresh Scheme for Dynamic Page Programming
Application:
10/119,273 →
Algorithm Dynamic Reference Programming
Application:
10/119,391 →
Frequency Measurement Circuit
Application:
10/088,605 →
Laser Thermal Annealing of Silicon Nitride for Increased Density and Etch Selectivity
Application:
10/096,741 →
Hard Mask Process for Memory Device Without Bitline Shorts
Application:
10/100,485 →
Method of Matching Core Cell and Reference Cell Source Resistances
Application:
10/083,789 →
Method of and Circuit for Controlling a Clock
Application:
10/073,490 →
Multiple-Bit Non-Volatile Memory Utilizing Non-Conductive Charge Trapping Gate
Application:
10/030,117 →
Overvoltage-Protective Device for Power System, Ac/Dc Converter and Dc/Dc Converter Constituting the Power System
Application:
10/041,594 →
Use of High-K Dielectric Materials in Modified Ono Structure for Semiconductor Devices
Application:
10/036,757 →
Flash Memory with Controlled Wordline Width
Application:
10/023,436 →
Reduction of Sector Connecting Line Capacitance Using Staggered Metal Lines
Application:
10/013,902 →
Flash Memory Array Architecture and Method of Programming, Erasing and Reading Thereof
Application:
10/013,993 →
Non Self-Aligned Shallow Trench Isolation Process with Disposable Space to Define Sub-Lithographic Poly Space
Application:
09/973,131 →
Process for Treating Ono Dielectric Film of a Floating Gate Memory Cell
Application:
09/927,134 →
Demand Usable Adapter Memory Access Management
Application:
09/912,954 →
Methods and Systems for a Shared Memory Unit with Extendable Functions
Application:
09/912,898 →
Multiple Block Sequential Memory Management
Application:
09/912,834 →
Dual Bit Isolation Scheme for Flash Memory Devices Having Polysilicon Floating Gates
Application:
09/833,307 →
Dual Bit Memory Device with Isolated Polysilicon Floating Gates
Application:
09/809,969 →
Piggyback Programming with Staircase Verify for Multi-Level Cell Flash Memory Designs
Application:
09/779,884 →