IP Library Granted Patent US 7,443,037
Granted Patent B2
US 7,443,037 · App. 11/278,421 · Granted Oct 28, 2008

Stacked integrated circuit package system with connection protection

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Quick Facts
Patent No.
US 7,443,037
App. No.
11/278,421
Filed
Apr 1, 2006
Granted
Oct 28, 2008
Kind
B2
Examiner
CHU, CHRIS C
Art Unit
2815
USPC
257/777
Abstract

A stacked integrated circuit package system is provided connecting an interconnect between a first integrated circuit device and a substrate, the first integrated circuit device on the substrate, applying a protective dot on the first integrated circuit device, mounting a second integrated circuit device, having an adhesive, on the protective dot, with the adhesive on the first integrated circuit device, connecting the second integrated circuit device and the substrate, and encapsulating the first integrated circuit device, the second integrated circuit device, and the interconnect.

Claims (46)

1. A stacked integrated circuit package process comprising:

connecting an interconnect between an interconnect stack on a first integrated circuit device and a substrate, the first integrated circuit device on the substrate;

applying a protective dot around the interconnect stack on the first integrated circuit device;

mounting a second integrated circuit device, having an adhesive, out of contact with the interconnect stack and on the protective dot, with the adhesive on the first integrated circuit device;

connecting the second integrated circuit device and the substrate; and

encapsulating the first integrated circuit device, the second integrated circuit device, and the interconnect.

2. The process as claimed in claim 1 wherein applying the protective dot on the first integrated circuit device includes applying the protective dot on the interconnect on the first integrated circuit device.

3. The process as claimed in claim 1 wherein applying the protective dot on the first integrated circuit device includes applying the protective dot on the interconnect on the first integrated circuit device and on a side of the first integrated circuit device next to the interconnect.

4. The process as claimed in claim 1 wherein applying the protective dot on the first integrated circuit device includes applying a plurality of protective dots on the first integrated circuit device.

5. The process as claimed in claim 1 wherein applying the protective dot on the first integrated circuit device includes applying a plurality of protective dots on the first integrated circuit device and the interconnect.

6. A stacked integrated circuit package process comprising:

connecting an interconnect between a ball stack on a first integrated circuit device having a peripheral bond pad and a substrate, the first integrated circuit device on the substrate;

applying a protective dot to cover the interconnect and the ball stack on the peripheral bond pad;

mounting a second integrated circuit device, having an adhesive, out of contact with the ball stack on the protective dot, with the adhesive on the first integrated circuit device;

connecting the second integrated circuit device and the substrate; and encapsulating the first integrated circuit device, the second integrated circuit device, and the interconnect.

7. The process as claimed in claim 6 wherein:

connecting the interconnect comprises:

forming the interconnect having a wire neck; and

applying the protective dot to cover the interconnect on the peripheral bond pad further comprises:

protecting the wire neck with the protective dot.

8. The process as claimed in claim 6 wherein connecting the interconnect between the first integrated circuit device having the peripheral bond pad and the substrate includes connecting the interconnect on the first integrated circuit device.

9. The process as claimed in claim 6 further comprising forming an additional protective dot as a spacer between the first integrated circuit device and the second integrated circuit device.

10. The process as claimed in claim 6 wherein applying the protective dot includes applying the protective dot comprised of an epoxy or a B-Stage material.

11. A stacked integrated circuit package system comprising:

an interconnect between an interconnect stack on a first integrated circuit device and a substrate, the first integrated circuit device on the substrate;

a protective dot around the interconnect stack on the first integrated circuit device;

a second integrated circuit device, having an adhesive, mounted out of contact with the interconnect stack and on the protective dot, with the adhesive on the first integrated circuit device and the second integrated circuit device connected to the substrate; and

an encapsulation to cover the first integrated circuit device, the second integrated circuit device, and the interconnect.

12. The system as claimed in claim 11 wherein the protective dot on the first integrated circuit device includes the protective dot on the interconnect on the first integrated circuit device.

13. The system as claimed in claim 11 wherein the protective dot on the first integrated circuit device includes the protective dot on the interconnect on the first integrated circuit device and on a side of the first integrated circuit device next to the interconnect.

14. The system as claimed in claim 11 wherein the protective dot on the first integrated circuit device includes a plurality of protective dots on the first integrated circuit device.

15. The system as claimed in claim 11 wherein the protective dot on the first integrated circuit device includes a plurality of protective dots on the first integrated circuit device and the interconnect.

16. The system as claimed in claim 11 wherein:

the interconnect is between the first integrated circuit device having a peripheral bond pad and the substrate, the first integrated circuit device on the substrate;

the protective dot on the first integrated circuit device is on the peripheral bond pad;

the second integrated circuit device, having the adhesive, is on the protective dot, with the adhesive on the first integrated circuit device and the protective dot covered, and the second integrated circuit device connected to the substrate;

the second integrated circuit device is connected to the substrate with a wire; and

the encapsulation to cover the first integrated circuit device, the second integrated circuit device, the interconnect, and the wire.

17. The system as claimed in claim 16 wherein:

the interconnect comprises:

the interconnect having a wire neck; and

the protective dot to cover the interconnect on the first integrated circuit device having the peripheral bond pad further comprises:

the wire neck on the peripheral bond pad protected with the protective dot.

18. The system as claimed in claim 16 wherein the interconnect between the first integrated circuit device having the peripheral bond pad and the substrate includes the interconnect on the first integrated circuit device.

19. The system as claimed in claim 16 further comprising an additional protective dot as a spacer between the first integrated circuit device and the second integrated circuit device.

20. The system as claimed in claim 16 wherein the protective dot comprises an epoxy or a B-Stage material.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319) Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064760/0986 →
RELEASE OF SECURITY INTEREST Recorded Jun 15, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052938/0305 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0319 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2006
From: KIM, HYUN JOUNG; JU, JONG WOOK; LIM, TAEG KI
To: STATS CHIPPAC LTD.
Reel/Frame 017404/0588 →