Semiconductor wafer scale package system
View Patent ↗A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the semiconductor substrate and the package substrate.
1. A semiconductor wafer scale packaging method comprising:
providing a semiconductor substrate, with an active side and a backside, having a through-hole via lined with a conductive coating, to fill the opening at the active side, formed directly on the semiconductor substrate;
forming a filled via by filling the through-hole via with a conductive material;
coupling a package substrate to the filled via including the active side away from the package substrate; and
singulating a chip scale package from the semiconductor substrate and the package substrate.
2. The method as claimed in claim 1 further comprising molding an encapsulant over the semiconductor substrate.
3. The method as claimed in claim 1 further comprising:
forming a semiconductor device on the semiconductor substrate having the active side;
forming a contact coupled to the semiconductor device on the active side; and
coupling the contact to the conductive coating in the through-hole via.
4. The method as claimed in claim 1 wherein filling the through-hole via with the conductive material including using a solder paste, a solder ball, or a curable adhesive.
5. The method as claimed in claim 1 further comprising:
forming a solder bump on a package substrate;
aligning the solder bump with the filled via; and
coupling the solder bump to the filled via with a reflow process.
6. A semiconductor wafer scale packaging method comprising:
providing a semiconductor substrate, with an active side and a backside, having a through-hole via lined with a conductive coating, to fill the opening at the active side, formed directly on the semiconductor substrate, including forming the through-hole via near the edge of a semiconductor device;
forming a filled via by filling the through-hole via with a conductive material including spraying or printing the conductive material;
coupling a package substrate to the filled via including the active side away from the package substrate by coupling all of the filled via on the semiconductor substrate to the package substrate; and
singulating a chip scale package from the semiconductor substrate and the package substrate including singulating the chip scale package.
7. The method as claimed in claim 6 further comprising:
molding an encapsulant over the semiconductor substrate including molding an epoxy molding compound; and
coupling system interconnects to the package substrate.
8. The method as claimed in claim 6 further comprising:
forming a semiconductor device on the semiconductor substrate having the active side;
forming a contact on the active side in which forming the contact includes forming the semiconductor device; and
coupling the contact to the conductive coating in the through-hole via in which coupling the contact includes electroplating the conductive coating.
9. The method as claimed in claim 6 wherein filling the through-hole via with the conductive material by using a solder paste a solder ball, or a curable adhesive includes using a eutectic, high temperature solder, or conductive epoxy for coupling the through-hole via to a central plane.
10. The method as claimed in claim 6 further comprising:
forming a solder bump on a package substrate including forming a solder ball or a solder column;
aligning the solder bump with the filled via including aligning the semiconductor substrate with the package substrate; and
forming a wafer scale package by coupling the solder bump to the filled via with a reflow process.