IP Library Granted Patent US 6,855,573
Granted Patent B2
US 6,855,573 · App. 10/251,231 · Granted Feb 15, 2005

Integrated circuit package and manufacturing method therefor with unique interconnector

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Quick Facts
Patent No.
US 6,855,573
App. No.
10/251,231
Granted
Feb 15, 2005
Kind
B2
Abstract

An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.

Claims (32)

1. A method for manufacturing an integrated circuit comprising:

providing a substrate having solder openings provided therein and a conductive layer thereon;

processing the conductive layer to form a plurality of pads over the solder openings in the substrate;

depositing a mask over the plurality of pads;

forming openings in the mask over at least two pads of the plurality of pads;

bonding an integrated circuit die over the substrate using a conductive adhesive; and

placing the conductive adhesive in the openings in conductive contact with the at least two pads of the plurality of pads.

2. The method as claimed in claim 1 wherein processing the conductive layer uses a metal layer bonded to or integrally deposited on the substrate.

3. The method as claimed in claim 1 wherein placing the conductive adhesive in the openings in the mask includes flowing the conductive adhesive under bonding pressure between the substrate and the integrated circuit die.

4. The method as claimed in claim 1 additionally comprising:

bonding a conductive plane over the substrate and under the integrated circuit die, the bonding using the conductive adhesive and providing conductive contact between the conductive adhesive and the conductive plane.

5. The method as claimed in claim 1 additionally comprising:

bonding a conductive plane over the substrate, the bonding using the conductive adhesive and providing conductive contact between the conductive adhesive and the conductive plane; and

bonding the integrated circuit die to the conductive plane.

6. A method for manufacturing an integrated circuit comprising:

providing a substrate having solder openings provided therein and a metal layer thereon;

processing the metal layer to form a plurality of pads over the solder openings in the substrate;

depositing a soldermask over the plurality of pads;

forming openings in the soldermask over at least two pads of the plurality of pads;

bonding an integrated circuit die over the substrate using a conductive die attach adhesive; and

placing the conductive die attach adhesive in the openings in the soldermask and in conductive contact with the at least two pads of the plurality of pads.

7. The method as claimed in claim 6 wherein processing the metal layer uses a metal layer bonded to or integrally deposited on the substrate.

8. The method as claimed in claim 6 wherein placing the conductive die attach adhesive in the openings in the soldermask includes flowing the conductive die attach adhesive under bonding pressure between a ground plane and the substrate.

9. The method as claimed in claim 6 wherein:

processing the metal layer forms a power cross-connect connecting two power pads of the plurality of pads; and

additionally comprising:

bonding a ground plane over the substrate and under the integrated circuit die, the ground plane, the bonding using the conductive die attach adhesive and providing conductive contact between the conductive die attach adhesive and the ground plane.

10. The method as claimed in claim 6 wherein:

processing the metal layer forms a power cross-connect connecting two power pads of the plurality of pads; and

additionally comprising:

bonding a ground plane over the substrate, the bonding using the conductive die attach adhesive and providing conductive contact between the conductive die attach adhesive and the ground plane; and

bonding the integrated circuit die to the ground plane.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0400. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064806/0593 →
RELEASE OF SECURITY INTEREST Recorded Jun 16, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052950/0497 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0400 →
CHANGE OF NAME Recorded Aug 6, 2015
From: ST ASSEMBLY TEST SERVICES LTD.
To: STATS CHIPPAC LTD.
Reel/Frame 036286/0590 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
CORRECTIVE TO CORRECT THE SECOND ASSIGNOR'S NAME AND THE ASSIGNEE'S ADDRESS PREVIOUSLY RECORDED AT REEL 013659 FRAME 0991. (ASSIGNMENT OF ASSIGNOR'S INTEREST) Recorded Jun 2, 2003
From: LI, JIAN JUN; SHIM, II KWON; BADAKERE, GURUPRASAD
To: ST ASSEMBLY TEST SERVICES LTD.
Reel/Frame 014116/0297 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2002
From: LI, JIAN JUN; SHIM, IL KWON; BADAKERE, GURUPRASAD
To: ST ASSEMBLY TEST SERVICES LTD.
Reel/Frame 013659/0991 →