IP Library Granted Patent US 6,943,092
Granted Patent B2
US 6,943,092 · App. 10/729,227 · Granted Sep 13, 2005

Methods of manufacturing semiconductor devices

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Quick Facts
Patent No.
US 6,943,092
App. No.
10/729,227
Granted
Sep 13, 2005
Kind
B2
Abstract

Methods of manufacturing semiconductor devices are disclosed. In a disclosed example, a multi-layered insulating structure is deposited on a semiconductor substrate, an opening is formed in the multi-layered insulating structure above the semiconductor substrate, and a trench is formed in the semiconductor substrate under the opening. Then, a groove is formed on an edge position of an intermediate layer of the multi-layered insulating structure by wet-etching the intermediate layer of the multi-layered insulating layer transversely using a pull back process. Then, a liner oxide layer is deposited on the groove and the trench. An oxide layer then fills the trench and the groove without generating voids or divots in the oxide layer of the trench.

Claims (5)

1. A method of manufacturing a semiconductor device comprising: forming a multi-layered insulating structure on a semiconductor substrate, the multi-layered insulating structure including an upper oxide layer, an intermediate nitride layer and a lower oxide layer; forming an opening in the insulating structure to expose a field region of the semiconductor substrate; forming a trench in the field region of the semiconductor substrate; forming a groove on an edge portion of the intermediate nitride layer of the multi-layered insulating structure; depositing a liner insulating layer in a desired thickness on surfaces of the trench, on an edge of the lower oxide layer, in the groove of the edge portion of the intermediate nitride layer, and on an edge of the upper oxide layer; and filling the groove and the trench with an oxide layer.

2. A method as defined in claim 1 , wherein the liner insulating layer comprises a liner oxide layer.

3. A method as defined in claim 2 , wherein the liner oxide layer is deposited by an atomic layer deposition (ALD) process.

4. A method as defined in claim 3 , wherein the liner oxide layer is deposited in a thickness of approximately 100 to 300 Å.

5. A method as defined in claim 4 , wherein the liner oxide layer is deposited at a temperature of approximately 250 to 350° C.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2019
From: DB HITEK CO., LTD.
To: COLUMBA TECHNOLOGIES INC.
Reel/Frame 049709/0857 →
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →
CHANGE OF NAME Recorded Jun 6, 2006
From: DONGBU ANAM SEMICONDUCTORS, INC
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017718/0964 →
MERGER Recorded May 31, 2005
From: DONGBU SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 016593/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2004
From: KIM, IN-SU
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 014887/0008 →