Die identification systems and methods
View Patent ↗Systems and methods are disclosed herein to provide die identification. For example, in accordance with an embodiment of the present invention, a wafer patterning technique is disclosed that provides multiple-exposure patterning to provide a unique identifying mark for each die on a wafer.
1. A method of providing identifying marks to die on a wafer, the method comprising:
providing an identification pattern on a first layer of the die; and
providing a marker on a second layer of the die using a multiple-exposure patterning process for the second layer, the second layer applied subsequent to the first layer, wherein a location of the marker relative to the identification pattern for each of the die indicates a corresponding location of the die on the wafer such that the corresponding location is known after separation of the die from the wafer, and wherein the providing of the marker comprises; applying a first image to the second layer except for a region above the identification pattern; and applying a second image to the second layer in the region above the identification pattern to provide the marker.
2. The method of claim 1 , wherein the identification pattern comprises a grid having a number of columns and a number of rows, the location of the marker at an intersection of one of the columns and one of the rows corresponds to the location of the die in a corresponding column and a corresponding row on the wafer.
3. The method of claim 1 , wherein the is formed of photoresist marker.
4. The method of claim 1 , wherein the applying the second image to provide the marker is performed in a different photo resist exposure pass for the second layer than the applying the first image to the second layer.
5. An integrated circuit comprising:
a die having at least a first layer and a second layer;
an identification pattern on the first layer of the die; and
a marker on the second layer of the die, wherein a location of the marker relative to the identification pattern indicates a corresponding location of the die on a wafer from which the die was separated; wherein the first and second layers are metal layers, the second layer above the first layer, and wherein the integrated circuit comprises: a circuit pattern on the second layer of the die, wherein the circuit pattern is on a portion of the second layer that is not directly over the identification pattern on the first layer of the die; and wherein the marker on the second layer of the die is positioned directly over the identification pattern on the first layer of the die, with the circuit pattern and the marker formed by a multiple-pass exposure process for the second layer.
6. The integrated circuit of claim 5 , wherein the identification pattern comprises a grid having a number of columns and a number of rows, the location of the marker at an intersection of one of the columns and one of the rows corresponds to the location of the die in a corresponding column and a corresponding row on the wafer from which the die was separated.
7. The integrated circuit of claim 5 , wherein the marker is made of photo resist second layer above the first layer, and wherein the integrated circuit further comprises.
8. An integrated circuit comprising:
a die having at least a first layer; and a marker on a second layer of the die; and
an identification pattern formed from photo resist on the first layer, wherein a location of the marker relative to the identification pattern indicates a previous location of the die on a wafer; wherein the marker on the second layer of the die is positioned relative to the identification pattern on the first layer of the die to provide the location of the die on the wafer from which the die was separated, and wherein the second layer of the die further includes a circuit pattern disposed on a portion of the second layer so as to not obscure the identification pattern on the first layer of the die relative to the marker on the second layer of the die.
9. The integrated circuit of claim 8 , wherein the identification pattern comprises a marker, a number, a character, a letter, and/or a grid.
10. The integrated circuit of claim 8 , wherein the identification pattern was formed during a multiple-exposure patterning.
11. The integrated circuit of claim 10 , wherein the marker is formed from photo resist.