III-V power field effect transistors
A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.
1. A semiconductor device comprising:
a III-VIII-V semiconductor substrate;
a III-VIII-V channel layer formed over said substrate;
a passivation layer comprising an insulating material formed over said channel layer;
source and drain regions comprising source and drain contacts formed over said channel layer the source region in electrical contact with a source contact and the drain region in electrical contact with a drain contact;
a gate electrode formed over the channel layer and in contact with the passivation layer wherein the device has a drift region which is the region between the gate electrode and the drain region;
a second electrode formed over and in contact with the passivation layer, the second electrode extending into the drift region;
wherein the passivation layer has an electrical thickness (E T ) that is calculated relative to a layer of Al 2 O 3 and is the thickness of the passivation layer (t) multiplied by the ratio of the dielectric constant of Al 2 O 3 to the average dielectric constant(K) of the passivation layer such that E T is less than about 0.3 μm and further that the passivation layer is an oxide formed by atomic layer deposition.
2. The device of claim 1 wherein the device is configured to have a peak field of 400 kV/cm at a V DS of 80 volts or less.
3. The device of claim 1 further comprising an overlapping gate in electrical contact with the gate and extending from the gate into the drift region, wherein the passivation layer is interposed between the portion of the overlapping gate extending into the drift region and the channel.
4. The device of claim 1 further comprising a field plate which is formed over the passivation layer in the drift region of the device, wherein the field plate is not in physical contact with either the drain contact or the gate.
5. The device of claim 3 wherein a p-type region is formed in a layer of single crystal III-VIII-V material and in proximity to the channel layer formed over the single crystal III-VIII-V layer, wherein the proximity of the p-type region is selected so that at least some portion of the p-type region is no more than about 0.5 μm from the device channel and wherein at least a portion of the p-type region extends from a region proximate the drain side of the device gate into the drift region of the device.
6. The device of claim 5 wherein the p-type region extends into the drift region by a distance that does not exceed about one-third the distance of the entire drift region.
7. The device of claim 6 wherein the total dopant dose in the p-type region is at least about 10 12 atoms/cm 2 .
8. The device of claim 7 wherein the p-type dopant is Beryllium.
9. The device of claim 4 wherein a p-type region is formed in the layer of single crystal III-VIII-V material in proximity to the channel layer formed thereover, wherein the proximity of the p-type region is selected so that at least some portion of the p-type region is no more than about 0.5 μm from the device channel and wherein at least a portion of the p-type region extends from a region underneath the device gate into the drift region of the device.
10. The device of claim 9 wherein the p-type region extends into the drift region by a distance that does not exceed about one-third the distance of the entire drift region.
11. The device of claim 1 wherein the passivation layer has an electrical thickness E T that is 0.2 μm or less.
12. The device of claim 1 wherein the substrate is selected from the group consisting of semi-insulating III-VIII-V substrates and p + III-VIII-V substrates.
13. The device of claim 12 wherein the device has a semi-insulating substrate and further comprises a hole-sink in proximity to the source contact.
14. The device of claim 13 further comprising a p + region is formed in the layer of single crystal III-VIII-V material in proximity to the channel layer formed thereover, wherein the proximity of the p-type region is selected so that at least some portion of the P + region is no more than about 0.5 μm from the device channel and wherein at least a portion of the p-type region extends from a region underneath the device gate into the drift region of the device and wherein the hole-sink is a p-type III-VIII-V region configured to contact the source region and the p + region.
15. A semiconductor device comprising:
a III-VIII-V semiconductor substrate;
a III-VIII-V channel layer formed over said substrate;
a passivation layer comprising an insulating material formed over said channel layer;
source and drain regions comprising source and drain contacts formed over said channel layer;
a gate electrode formed over the channel layer and in contact with the passivation layer wherein the device has a drift region which is the region between the gate electrode and the drain region;
a second electrode formed over and in contact with the passivation layer, the second electrode extending into the drift region;
wherein a p-type region is formed in the layer of single crystal III-VIII-V material in proximity to the channel layer formed thereover, wherein the proximity of the p-type region is selected so that at least some portion of the p-type region is no more than about 0.5 μm from the device channel and wherein at least a portion of the p-type region extends from a region underneath the device gate into the drift region of the device.
16. The device of claim 15 wherein the passivation layer has an electrical thickness (E T ) that is the product of the dielectric constant of Al 2 O 3 and the thickness of the passivation layer (t) divided by the dielectric constant (K) of the passivation layer (E T =K A1203 ·t)/K) such that E T is less than about 0.3 μm and is an oxide formed by atomic layer deposition.
17. The device of claim 16 wherein the device is configured to have a peak field of 400 kV/cm at a V DS of 80 volts or less.
18. The device of claim 15 wherein the p-type region extends into the drift region by a distance that does not exceed about one-third the distance of the entire drift region.
19. The device of claim 16 wherein the total dopant dose in the p-type region is at least about 10 12 atoms/cm 2 .
20. The device of claim 19 wherein the p-type dopant is Beryllium.
21. The device of claim 15 wherein the substrate is selected from the group consisting of semi-insulating III-VIII-V substrates and p + III-VIII-V substrates.
22. The device of claim 21 wherein the device has a semi-insulating substrate and further comprises a hole-sink in proximity to the source.
23. The device of claim 22 further comprising a p-type region formed in the layer of single crystal III-VIII-V material in proximity to the channel layer formed thereover, wherein the proximity of the p-type region is selected so that at least some portion of the p-type region is no more than about 0.5 μm from the device channel and wherein at least a portion of the p-type region extends from a region underneath the device gate into the drift region of the device and wherein the hole-sink is a p-type GaAs region configured to contact the source region and the p-type region.