Semiconductor devices and methods of fabricating the same
View Patent ↗Semiconductor devices and methods of fabricating the same are disclosed. A disclosed method comprises: partially forming a first gate stack; partially forming a second gate stack adjacent the first gate stack; forming a first interlayer dielectric; and completing the formation of the first and second gate stacks after the first interlayer dielectric has filled a distance between the first and second gate electrodes.
1. A method of fabricating a semiconductor device comprising:
forming a first gate electrode on an active region of a semiconductor substrate;
forming an etch protective layer on the first gate electrode;
forming a first interlayer dielectric over the first gate electrode;
forming an opening through the first interlayer dielectric and the etch protective layer, exposing a top surface of the first gate electrode;
forming a second gate electrode on the first gate electrode by filling the opening with a conductive material, wherein the first and second gate electrodes together comprise a gate stack;
forming a second interlayer dielectric over both the second gate electrode and the first interlayer dielectric;
forming an opening through the second interlayer dielectric exposing a top portion of the second gate electrode;
filling the opening to form a contact plug; and
forming a metal interconnect over the second interlayer dielectric, wherein the metal interconnect is electrically connected to the second gate electrode by the contact plug.
2. The method as defined by claim 1 , wherein the first gate electrode has a thickness which is between 10% and 90% of a thickness of the gate stack.
3. The method as defined by claim 1 , wherein the second gate electrode comprises polysilicon, tungsten, aluminum, or copper.
4. The method as defined by claim 1 , wherein the etch protective layer is an oxide layer formed by a CVD process.
5. A method of fabricating a semiconductor device comprising:
forming first and second gate electrodes on a semiconductor substrate, the first and second gate electrodes being separated by a distance;
forming an etch protective layer on the first and second gate electrodes;
forming a first interlayer dielectric over the first and second gate electrodes, the first interlayer dielectric filling the distance between the first and second gate electrodes;
forming first and second openings through the interlayer dielectric and the etch protective layer, the first opening exposing a top surface of the first gate electrode and the second opening exposing a top surface of the second gate electrode;
forming a third gate electrode on the first gate electrode by filling the first opening with a conductive material;
forming a fourth gate electrode on the second gate electrode by filling the second opening with a conductive material; wherein the first and third gate electrodes together comprise a first gate stack and the second and fourth gate electrodes together comprise a second gate stack;
forming a second interlayer dielectric over both the third and fourth gate electrodes and the first interlayer dielectric;
forming third and fourth openings through the second interlayer dielectric respectively exposing top portions of the third and fourth gate electrodes;
filling the third and fourth opening to form first and second contact plugs; and
forming a metal interconnect over the second interlayer dielectric, wherein the metal interconnect is electrically connected to the third gate electrode by the first contact plug.
6. The method as defined by claim 5 , wherein the first gate electrode has a thickness which is between 10% and 90% of a thickness of the first gate stack.
7. The method as defined by claim 5 , wherein the second gate electrode comprises polysilicon, tungsten, aluminum, or copper.
8. The method as defined by claim 5 , wherein the etch protective layer is an oxide layer formed by a CVD process.
9. A method of forming first and second adjacent gate stacks comprising:
forming a first gate electrode having a thickness less than a desired thickness of the first gate stack;
forming a second gate electrode having a thickness less than a desired thickness of the second gate stack, the first and second gate electrodes being separated by a distance;
forming an etch protective layer on the first and second gate electrodes;
forming a first interlayer dielectric over the first and second gate electrodes to fill the distance between the first and second gate electrodes;
forming first and second openings through the first interlayer dielectric and the etch protective layer, the first opening exposing a top surface of the first gate electrode and the second opening exposing a top surface of the second gate electrode;
forming a third gate electrode on the first gate electrode to form the first gate stack;
forming a fourth gate electrode on the second gate electrode to form the second gate stack;
forming a second interlayer dielectric over both the third and fourth gate electrodes and the first interlayer dielectric;
forming third and fourth openings through the second interlayer dielectric respectively exposing top portions of the third and fourth gate electrodes;
filling the third and fourth opening to form first and second contact plugs; and
forming a metal interconnect over the second interlayer dielectric, wherein the metal interconnect is electrically connected to the third gate electrode by the first contact plug.
10. The method as defined by claim 9 , wherein the etch protective layer is an oxide layer formed by a CVD process.