Method for forming wordlines having irregular spacing in a memory array
View Patent ↗According to one exemplary embodiment, a method of fabricating memory array includes forming a number of hard mask lines and at least one dummy hard mask line on a layer of polysilicon, where the at least one dummy hard mask line is situated in a bitline contact region of the memory array. The method further includes removing the at least one dummy hard mask line. According to this embodiment, the method further includes forming a number of wordlines, where each of the wordlines is situated under one of the hard mask lines, and where the bitline contact region causes an irregularity in spacing of the wordlines. Two of the wordlines are situated adjacent to the bitline contact region such that the spacing between the two wordlines is substantially equal to a width of the bit line contact region.
1. A method of fabricating a memory array, said method comprising:
forming a plurality of hard mask lines and at least one dummy hard mask line on a layer of polysilicon, said at least one dummy hard mask line being situated in a bitline contact region of said memory array;
forming a mask over said layer of polysilicon, wherein said mask covers said plurality of hard mask lines and does not cover said at least one dummy hard mask line;
removing said at least one dummy hard mask line;
forming a plurality of wordlines, each of said plurality of wordlines being situated under one of said plurality of hard mask lines;
said method thereby controlling a spacing of said plurality of wordlines in said bitline contact region.
2. The method of claim 1 further comprising a step of forming a first plurality of resist lines on a hard mask layer prior to said step of forming said plurality of hard mask lines, wherein at least one of said first plurality of resist lines is situated in said bitline contact region.
3. The method of claim 2 wherein said first plurality of resist lines are evenly spaced.
4. The method of claim 1 wherein said at least one dummy hard mask line comprises two dummy hard mask lines.
5. The method of claim 2 wherein said at least one resist line comprises two resist lines.
6. The method of claim 1 wherein two of said plurality of wordlines are situated adjacent to said bitline contact region, where a distance between said two of said plurality of wordlines is substantially equal to a width of said bit line contact region.
7. The method of claim 2 wherein a width of each of said first plurality of resist lines is between approximately 70.0 nanometers and approximately 80.0 nanometers.
8. The method of claim 2 wherein said first plurality of resist lines comprises a second plurality of resist lines, wherein each of said second plurality of resist lines determines a width of one of said plurality of hard mask lines.
9. The method of claim 1 wherein said layer of polysilicon is situated over an ONO stack.
10. A method of fabricating a memory array, said method comprising:
forming a first plurality of resist lines on a hard mask layer situated on a layer of polysilicon, at least one of said first plurality of resist lines being situated in a bitline contact region of said memory array;
forming a plurality of hard mask lines and at least one dummy hard mask line on said layer of polysilicon, said at least one dummy hard mask line being situated in said bitline contact region;
forming a mask over said layer of polysilicon, wherein said mask covers said plurality of hard mask lines and does not cover said at least one dummy hard mask line;
removing said at least one dummy hard mask line;
forming a plurality of wordlines, each of said plurality of wordlines being situated under one of said plurality of hard mask lines;
said method thereby controlling a spacing of said plurality of wordlines in said bitline contact region.
11. The method of claim 10 wherein said first plurality of resist lines are evenly spaced.
12. The method of claim 10 wherein said at least one dummy hard mask line comprises two dummy hard mask lines.
13. The method of claim 10 wherein said at least one resist line comprises two resist lines.
14. The method of claim 10 wherein said first plurality of resist lines comprises a second plurality of resist lines, wherein each of said second plurality of resist lines is situated outside of said bitline contact region, wherein said at least one resist line has a width greater than a width of each of said second plurality of resist lines.
15. The method of claim 10 wherein said first plurality of resist lines comprises a second plurality of resist lines, wherein each of said second plurality of resist lines determines a width of one of said plurality of hard mask lines.
16. The method of claim 10 wherein a distance between two of said wordlines is substantially equal to a width of said bit line contact region.
17. The method of claim 10 wherein a width of each of said first plurality of resist lines is between approximately 70.0 nanometers and approximately 80.0 nanometers.
18. The method of claim 10 wherein said layer of polysilicon is situated over an ONO stack.