IP Library Granted Patent US 7,773,680
Granted Patent B2
US 7,773,680 · App. 11/254,359 · Granted Aug 10, 2010

System and method for providing 3-dimensional joint interleaver and circulation transmissions

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Quick Facts
Patent No.
US 7,773,680
App. No.
11/254,359
Granted
Aug 10, 2010
Kind
B2
Abstract

System performance in wireless communication is improved by increasing diversity in time, space and frequency. Information to be transmitted is processed by a convolution encoder to produce encoded bits. The encoded bits are interleaved and mapped to subcarriers. Symbols are created from the subcarriers and the symbols are transmitted so as to increase diversity in time, space and frequency. Circulation transmission in addition to interleaving is used to increase diversity. For example, circulation transmission can be symbol based or subcarrier based.

Claims (686)

1. A three-Dimensional (3D) interleaver for interleaving an input stream in an Orthogonal-Frequency-Division-Multiplexing (OFDM) based Multiple-Input-Multiple-Output (MIMO) system, the 3D interleaver configured to:

receive an input bit stream A(k), k=0, 1, 2, . . . , N CBPS ×N I −1, where N CBPS is the number of input bits per OFDM symbol, N I is the number of OFDM symbols per 3D interleaver;

select two parameters N row and N column , where N row ×N column =N CBPS ;

form a 3D structure, the 3D structure having N I ×N row ×N column empty cells, dimensions of the 3D structure being N I , N row and N column respectively;

write each input bit A(k) to each cell of the 3D structure, position of each cell in the 3D structure being defined by three co-ordinates, x, y, and z, where 0≦x≦N column −1, 0≦y≦N I −1, and 0≦z≦N row −1;

interleave the input bit stream A(k), k=0, 1, 2, . . . , N CBPS ×N I −1 into N I groups of cells in a 3D structure, each group being associated with one OFDM symbol, wherein consecutive input bits are assigned to different groups of cells to allow for the two consecutive input bits to be transmitted in different OFDM symbols; and

output an interleaved bit stream B(j), j=0, 1, 2, . . . , N CBPS ×N I −1, from the 3D structure.

2. The 3D interleaver of claim 1 , wherein each input bit A(k) is randomly written into one empty cell of the 3D structure.

3. The 3D interleaver of claim 1 , wherein each interleaved bit B(j) is randomly read from the 3D structure, each cell being read only once.

4. The 3D interleaver of claim 1 , wherein a first input bit A(m) and a second input bit A(n) are modulated to the same subcarrier of different OFDM symbols, the first input bit A(m) and the second input bit A(n) having a separation of at least N column bits, where m,n=0, 1, 2, . . . , N CBPS ×N I −1.

5. The 3D interleaver of claim 1 , wherein two consecutive input bits A(k) and A(k+1) are modulated to a first subcarrier and a second subcarrier respectively, the first and the second subcarriers being in different OFDM symbols and having at least a separation of N SCPC subcarriers, where N SCPC =N row /N BPSC , and N BPSC is the number of bits per subcarrier.

6. The 3D interleaver of claim 1 , wherein a first input bit A(i) and a second input bit A(j) are modulated to two consecutive subcarriers of the same OFDM symbol, the first encoded bit A(i) and the second encoded bit A(j) having a separation of at least N I ×N column bits.

7. The 3D interleaver of claim 1 , wherein the three co-ordinates x, y, z of the 3D structure are represented by the following equations:

x

=

k

mod

(

N

column

)

;

y

=

floor

(

k

N

column

)

mod

(

N

I

)

;

z

=

floor

[

(

k

N

column

N

I

)

and the interleaved bit stream B(j) is obtained according to the following equation:

j

=

z

+

x

·

(

(

N

CBPS

)

N

column

)

+

N

CBPS

·

(

(

y

-

x

)

mod

(

N

I

)

)

where

j

=

0

,

1

,

2

,

,

N

CBPS

N

I

-

1.

8. The 3D interleaver of claim 1 , wherein the three co-ordinates x, y, z of the 3D structure are represented by the following equations:

x

=

k

mod

(

N

column

)

;

y

=

floor

(

k

N

column

)

mod

(

N

I

)

;

z

=

floor

[

(

k

N

column

N

I

)

and the interleaved bit stream B(j) is obtained according to the following equation:

i

=

z

+

x

·

(

N

CBPS

N

column

)

+

N

CBPS

·

(

(

y

-

x

)

mod

(

N

I

)

)

;

j

=

N

CBPS

[

floor

(

i

N

CBPS

)

]

+

s

·

[

floor

(

i

mod

(

N

CBPS

)

s

)

]

+

[

(

i

mod

(

N

CBPS

)

)

+

N

CBPS

-

floor

{

N

column

(

i

mod

(

N

CBPS

)

)

N

CBPS

}

]

mod

(

s

)

where

s

=

max

(

N

BPSC

/

2

,

1

)

,

i

,

j

=

0

,

1

,

,

N

CBPS

N

I

-

1.

9. The 3D interleaver of claim 1 , wherein the three co-ordinates x, y, z of the 3D structure are represented by the following equations:

j

=

N

CBPS

[

floor

(

i

N

CBPS

)

]

+

s

·

[

floor

(

i

mod

(

N

CBPS

)

s

)

]

+

[

(

i

mod

(

N

CBPS

)

)

+

N

CBPS

-

floor

{

N

column

(

i

mod

(

N

CBPS

)

)

N

CBPS

}

]

mod

(

s

)

where

s

=

max

(

N

BPSC

/

2

,

1

)

,

i

,

j

=

0

,

1

,

,

N

CBPS

N

I

-

1.

and the interleaved bit stream B(j) is obtained according to the following equation:

j

=

z

+

x

·

(

(

N

CBPS

)

N

column

)

+

N

CBPS

·

(

(

y

-

x

)

mod

(

N

I

)

)

where

j

=

0

,

1

,

2

,

,

N

CBPS

N

I

-

1.

10. The 3D interleaver of claim 1 , wherein the three co-ordinates x, y, z of the 3D structure are represented by the following equations:

x

=

k

mod

(

N

column

)

;

y

=

floor

(

k

N

column

)

mod

(

N

I

)

;

z

=

floor

[

(

k

N

column

N

I

)

+

y

·

N

BPSC

]

mod

(

N

CBPS

N

column

)

;

and the interleaved bit stream B(j) is obtained according to the following equation:

i

=

z

+

x

·

(

N

CBPS

N

column

)

+

N

CBPS

·

(

(

y

-

x

)

mod

(

N

I

)

)

;

j

=

N

CBPS

[

floor

(

i

N

CBPS

)

]

+

s

·

[

floor

(

i

mod

(

N

CBPS

)

s

)

]

+

[

(

i

mod

(

N

CBPS

)

)

+

N

CBPS

-

floor

{

N

column

(

i

mod

(

N

CBPS

)

)

N

CBPS

}

]

mod

(

s

)

where

s

=

max

(

N

BPSC

/

2

,

1

)

,

i

,

j

=

0

,

1

,

,

N

CBPS

N

I

-

1.

11. The 3D interleaver of claim 1 , wherein the 3D structure comprises a 3D block.

12. A method for interleaving a plurality of input data bits in an Orthogonal-Frequency-Division-Multiplexing (OFDM) based Multiple-input-multiple-output (MIMO) system, the method comprising:

receiving an input bit stream;

writing the received input bit stream to a 3D structure;

selecting three parameters N I , N row and N column , where N row ×N column =N CBPS , N CBPS is the number of input bits per OFDM symbol, N I is the number of OFDM symbols per 3D interleaver;

interleaving the input bit stream to generate a corresponding interleaved bit stream; and

outputting the interleaved bit stream from the 3D structure, wherein two consecutive input bits of the input bit stream are transmitted in different OFDM symbols simultaneously.

13. The method of claim 12 further comprising forming the 3D structure, the 3D structure having N I ×N row ×N column empty positions, dimensions of the 3D structure being N I , N row and N column respectively.

14. The method of claim 13 further comprising writing each input bit to each position of the 3D structure, the position of each input bit in the 3D structure being defined by three co-ordinates, x, y, and z, where 0≦x≦N column −1, 0≦y≦N I −1, and 0≦z≦N row −1.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2015
From: MICROCHIP TECHNOLOGY (BARBADOS) II INCORPORATED
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 036631/0442 →
MERGER Recorded Sep 6, 2015
From: ISSC TECHNOLOGIES CORP.
To: MICROCHIP TECHNOLOGY (BARBADOS) II INCORPORATED
Reel/Frame 036561/0944 →
CHANGE OF NAME Recorded Jun 24, 2010
From: INTEGRATED SYSTEM SOLUTION CORP
To: ISSC TECHNOLOGIES CORP.
Reel/Frame 024592/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2006
From: CHEN, JENG-HONG; KIM, PANSOP
To: WINBOND ELECTRONICS CORPORATION
Reel/Frame 018305/0882 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2006
From: WINBOND ELECTRONICS CORP.
To: INTEGRATED SYSTEM SOLUTION CORP.
Reel/Frame 017711/0367 →