Granted Patent B2

US 7,443,039 · App. 11/306,352 · Granted Oct 28, 2008

Abstract

Claims (46)

1. An integrated circuit package comprising:

a substrate having first and second contact pads thereon exposed through a passivation layer thereon;

a first metallurgy layer over the second contact pad separated from the substrate by the passivation layer;

a second metallurgy layer over the first metallurgy layer over the second contact pad and separated from the substrate; and

a protective layer only over the first contact pad without the first and second metallurgy layers thereover.

2. The package as claimed in claim 1 wherein:

the protective layer is a compound of an etchant component reacted with the material of the first contact pad.

3. The package as claimed in claim 1 further comprising:

a cap layer over the first and second contact pads;

and wherein:

the protective layer is a compound of an etchant component with the material of the first contact pad.

4. The package as claimed in claim 1 further comprising:

a wire-bond pad semiconductor die or package substrate wire-bonded to the first contact pad;

a bump pad semiconductor die or package substrate ball bonded to the second metallurgy layer over the second contact pad;

a semiconductor die or package substrate connected to the substrate; and

an encapsulant encapsulating at least a portion of the substrate.

5. The package as claimed in claim 1 wherein:

the substrate comprises at least one of the first and second contact pads using aluminum, an alloy thereof, or a compound thereof;

the first metallurgy layer uses titanium, an alloy thereof, or a compound thereof;

the second metallurgy layer uses at least one of nickel, vanadium, copper, an alloy thereof and a compound thereof; and

the protective layer uses aluminum fluoride.

6. An integrated circuit package comprising:

a substrate having first and second contact pads thereon exposed through a passivation layer thereon;

a first under bump metallurgy layer over the second contact pad separated from the substrate by the passivation layer;

a second under bump metallurgy layer over the first under bump metallurgy layer and separated from the substrate;

a protective layer only over the first contact pad without the first and second under bump metallurgy layers thereover; and

additional substrates connected to the substrate by the first and second contact pads.

7. The package as claimed in claim 6 wherein:

the substrate comprises the first contact pad using aluminum, an alloy thereof, or a compound thereof;

the first under bump metallurgy layer uses titanium, an alloy thereof, or a compound thereof; and

the second under bump metallurgy layer uses at least one of nickel, vanadium, copper, an alloy thereof and a compound thereof.

8. The package as claimed in claim 6 further comprising:

a cap layer over the substrate under the first under bump metallurgy layer, the cap layer uses at least one of aluminum, copper, an alloy thereof, and a compound thereof;

and wherein:

the protective layer is a compound of fluorine and aluminum.

9. The package as claimed in claim 6 wherein:

the additional substrates comprise:

a wire bond pad semiconductor die or package substrate wire bonded to the first contact pad; and

a bump pad semiconductor die or package substrate ball bonded to the second under bump metallurgy layer over the second contact pad.

10. The package as claimed in claim 6 wherein:

the additional substrates comprise:

a package substrate connected to the substrate by a wire bond;

a further substrate connected to the substrate by a ball bond; and

further comprising:

an encapsulant encapsulating the substrate; and

solder balls on the package substrate.

Assignments (6)