COL-TSOP with nonconductive material for reducing package capacitance
A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include one or more semiconductor die having die attach pads along a single side. The leadframe may include a plurality of elongated electrical leads, extending from a first side of the leadframe, beneath the die, and terminating at a second side of the leadframe adjacent to the bond pads along the single edge of the die. The leadframe may further include a dielectric spacer layer on the elongated leads. Spacing the semiconductor die from the elongated leads using the spacer layer reduces the parasitic capacitance and/or inductance of the semiconductor package formed thereby.
1. In a chip-on-lead semiconductor package having a semiconductor die affixed to a leadframe without a leadframe die paddle, a method of reducing capacitance and/or inductance, comprising the steps of:
(a) affixing a spacer layer in the form of one of a polyimide tape or a dielectric film to a first surface of the leadframe;
(b) affixing the semiconductor die to the spacer layer using an adhesive layer separate from the spacer layer;
(c) affixing a rigid member, separate from the leadframe, first spacer layer and adhesive layer, to a second surface of the leadframe, the second surface of the leadframe being opposite the first surface of the leadframe; and
(d) encapsulating the semiconductor package within mold compound with the spacer layer and semiconductor die rigid member and portions of the leadframe completely encapsulated within the mold compound.
2. The method of claim 1 , said step a) further comprising the step of affixing a spacer layer having a thickness of between 2 mils and 8 mils to the leadframe.
3. In a chip-on-lead semiconductor package having a semiconductor die affixed to a leadframe without a leadframe die paddle, the semiconductor die having die bond pads along a single side and the leadframe having elongated leads to connect to the die bond pads on the single side, a method of reducing capacitance and/or inductance between the semiconductor die and the elongated leads, comprising the steps of:
(a) affixing an adhesive spacer layer formed of polyimide tape having a thickness of between 3 mils and 5 mils to a first surface of the elongated leads;
(b) affixing the semiconductor die to the spacer layer using an adhesive layer separate from the polyimide tape;
(c) affixing a rigid member to a second surface of the elongated leads, the second surface of the elongated leads being opposite the first surface of the elongated leads, the rigid member being separate from the leadframe, adhesive spacer layer and adhesive layer and the rigid member not being a die paddle or a heat sink; and
(d) encapsulating the semiconductor package within mold compound, a bottom surface of the rigid member being exposed through the mold compound.
4. The method of claim 3 , further comprising:
(e) affixing a second adhesive spacer layer formed of polyimide tape having a thickness of between 3 mils and 5 mils between the second surface of the elongated leads and the rigid member.
5. In a chip-on-lead semiconductor package having a semiconductor die affixed to a leadframe without a leadframe die paddle, a method of reducing capacitance and/or inductance, comprising the steps of:
a) affixing a first spacer layer having a thickness of between 2 mils and 8 mils to a first surface of the leadframe;
b) affixing the semiconductor die to the first spacer layer using an adhesive layer separate from the spacer layer, the first spacer layer reducing the parasitic capacitance of the semiconductor package;
c) affixing a second spacer layer having a thickness of between 2 mils and 8 mils to a second surface of the leadframe; and
d) affixing a structural member to the second spacer layer.
6. The method of claim 5 , said step a) of affixing a first spacer layer having a thickness of between 2 mils and 8 mils to the leadframe comprising the step of affixing a polyimide tape to the leadframe.
7. The method of claim 5 , said step a) of affixing a first spacer layer having a thickness of between 2 mils and 8 mils to the leadframe comprising the step of affixing a dielectric film to the leadframe.
8. The method of claim 5 , said step a) of affixing a first spacer layer having a thickness of between 2 mils and 8 mils to the leadframe comprising the step affixing a first spacer layer having a thickness of between 3 mils and 5 mils to the leadframe.
9. The method of claim 5 , said step c) of affixing a second spacer layer having a thickness of between 2 mils and 8 mils to the leadframe comprising the step of affixing a polyimide tape to the leadframe.
10. The method of claim 5 , said step c) of affixing a second spacer layer having a thickness of between 2 mils and 8 mils to the leadframe comprising the step of affixing a dielectric film to the leadframe.
11. The method of claim 5 , said step c) of affixing a second spacer layer having a thickness of between 2 mils and 8 mils to the leadframe comprising the step of affixing a second spacer layer having a thickness of between 3 mils and 5 mils to the leadframe.
12. A chip-on-lead semiconductor package, comprising:
a leadframe including elongated leads, the elongated leads having a first surface and a second surface opposed to the first surface;
a first spacer layer affixed to the first surface of the elongated leads using an adhesive layer separate from the first spacer layer, the first spacer layer reducing the parasitic capacitance of the semiconductor package;
one or more semiconductor die;
an adhesive layer for affixing the one or more semiconductor die to the first spacer layer;
a second spacer layer affixed to the second surface of the elongated leads; and
a silicon structural member affixed to the second spacer layer.
13. A chip-on-lead semiconductor package as recited in claim 12 , the first and second spacer layers comprising a polyimide adhesive tape.
14. A chip-on-lead semiconductor package as recited in claim 12 , the first and second spacer layers comprising one of an epoxy resin or bismaleimide triazine.
15. A chip-on-lead semiconductor package as recited in claim 12 , the first spacer layer comprising a pad affixed to the first surface of the elongated leads.
16. A chip-on-lead semiconductor package as recited in claim 12 , the first spacer layer comprising two or more strips affixed to the first surface of the elongated leads.
17. A chip-on-lead semiconductor package as recited in claim 12 , the second spacer layer comprising a pad affixed to the second surface of the elongated leads.
18. A chip-on-lead semiconductor package as recited in claim 12 , the second spacer layer comprising two or more strips affixed to the second surface of the elongated leads.
19. A chip-on-lead semiconductor package as recited in claim 12 , the semiconductor package comprising a plastic small outlined package.
20. A chip-on-lead semiconductor package as recited in claim 12 , the semiconductor package comprising a thin small outlined package.
21. A chip-on-lead semiconductor package as recited in claim 12 , the semiconductor package comprising a shrink small outline package.