Dual layer barrier film techniques to prevent resist poisoning
View Patent ↗Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.
1. A dual damascene semiconductor device structure comprising:
a substrate having a metallization layer formed thereon;
a first barrier layer containing silicon carbide and nitrogen formed on the substrate such that it covers at least a portion of the metallization layer;
a nitrogen-free second barrier layer formed on top of the first barrier layer to reduce the effects of nitrogen poisoning in subsequently formed photoresist layers;
a first low-k dielectric layer formed on the second barrier layer;
an etch stop layer deposited on top of the second barrier layer;
a second low-k dielectric layer deposited on top of the etch stop layer;
a via formed such that it extends through the first and second low-k dielectric layers but does not substantially extend into the underlying barrier layers;
a trench formed such that it extends through the second low-k dielectric layer but not into the first low-K dielectric layer; and
a conductive material filling the via and trench but does not substantially extend into the underlying barrier layers.
2. The dual damascene semiconductor device structure of claim 1
wherein the nitrogen-free second barrier layer on top of the first barrier layer comprises a nitrogen-free silicon carbide layer.
3. The dual damascene semiconductor device structure of claim 1
wherein a first barrier layer containing silicon carbide and nitrogen is deposited using a PECVD process and one of NH 3 , N 2 , and N 2 O as a chemical precursor to supply the nitrogen and a nitrogen-free second barrier layer is formed by turning off the supply of nitrogen.
4. The dual damascene semiconductor device structure of claim 1
wherein the nitrogen-free second barrier layer is formed by injecting an SiH x (CH 3 ) y gas, where x is chosen in the range of 1 to 4, and x+y=4.
5. The dual damascene semiconductor device structure of claim 1
further comprising copper deposited in the trench and the via.
6. The dual damascene semiconductor device structure of claim 5 wherein the copper is deposited by an electrochemical process to fill the via and the trench.