Data register with efficient erase, program verify, and direct bit-line memory access features
A programmable memory device circuit comprising a sense and programming circuit, a latch circuit, a verify circuit for coupling the latch circuit logic value to a shared indicator line, and a direct memory access circuit coupled to the verify circuit. The DMA circuit couples a bit line to the verify circuit, and the verify circuit couples the direct memory access circuit to a shared verify indicator and DMA line.
1. A programmable memory device circuit comprising:
a sense and programming circuit configured to be selectively coupled to a memory tell bit line;
a latch circuit coupled to the sense and program circuit, the latch circuit configured to store a predetermined logic value;
a verify circuit coupled to the latch circuit, the verify circuit configured to couple the latch circuit logic value to a shared indicator line;
a direct memory access circuit coupled to the verify circuit, the direct memory access circuit configured to couple a bit line to the verify circuit; and
the verify circuit being further configured to couple the direct memory access circuit to the shared indicator line.
2. The programmable memory device of claim 1 , wherein the latch circuit includes tri-state devices that enable or disable the latch circuit.
3. The programmable memory device of claim 1 , wherein the verify circuit is shared between a plurality of data register circuits.
4. The programmable memory device of claim 1 , wherein the verify circuit, in combination with the direct memory access circuit, is configured to couple the bit line to the shared indicator line.
5. The programmable memory device of claim 1 , wherein the verify circuit, in combination with the direct memory access circuit, is configured to couple a ground voltage to a control input of a verify driver transistor,
6. The programmable memory device of claim 1 , wherein a portion of the verify circuit is discharged prior to coupling the latch circuit predetermined logic value to a shared indicator line.
7. Thee programmable memory device of claim 1 , further comprising a set and reset transistor coupled to the latch circuit and verify circuit.
8. The programmable memory device of claim 1 , further comprising a bit line charge transistor coupled to the bit line and coupled to a charge voltage source.
9. A programmable memory device comprising:
a sense and programming circuit configured to be selectively coupled to a memory cell bit line;
a latch circuit coupled to the sense and program circuit, the latch circuit configured to store a predetermined logic value;
a verify circuit coupled to the latch circuit, the verify circuit including a verify driver transistor coupled to a shared indicator line and a verify discharge transistor configured to discharge a control input of the verify driver transistor;
a direct memory access (DMA) circuit including a DMA pass transistor coupled to the verify discharge transistor and also coupled to a selected bit line, the direct memory access circuit further including a DMA discharge transistor coupled to the verify discharge transistor and also coupled to a ground voltage and configured to couple the verify discharge transistor to the ground voltage; and
the verify circuit and the direct memory access circuit each being configured to selectively couple the selected bit line to the shared indicator line.
10. The programmable memory device of claim 9 , wherein the latch circuit includes tri-state devices that enable or disable the latch circuit.
11. The programmable memory device of claim 9 , wherein the verify circuit is shared between a plurality of data register circuits.
12. The programmable memory device of claim 9 , wherein the verify circuit, in combination with the direct memory access circuit, is configured to couple the ground voltage to the control input of the verify driver transistor.
13. The programmable memory device of claim 9 wherein the verify driver transistor is configured to couple the latch circuit predetermined logic value to the shared indicator line.
14. The programmable memory device of claim 9 , wherein the verify discharge transistor discharges the control input of the verify driver transistor prior to coupling the latch circuit predetermined logic value to a shared indicator line.
15. The programmable memory device of claim 9 , further comprising a set and reset transistor coupled to the latch circuit and verify circuit.
16. The programmable memory device of claim 9 , further comprising a bit line charge transistor coupled to the bit line and also coupled to a charge voltage source.
17. A method of controlling a programmable memory device, the method comprising:
activating a verify discharge transistor;
activating a DMA discharge transistor;
discharging a control input of a verify driver transistor;
deactivating the verify discharge transistor and the DMA discharge transistor; and
activating simultaneously, the verify driver transistor and a direct memory access (DMA) pass transistor, thereby coupling a selected bit line to a shared indicator line.
18. The method of controlling a programmable memory device of claim 17 , further comprising pre-charging the indicator line to a high logic state.
19. The method of controlling a programmable memory device of claim 17 , further comprising sharing the verify discharge transistor, the DMA discharge transistor, and the verify driver transistor between a plurality of memory data register circuits.
20. The method of controlling a programmable memory device of claim 17 , wherein discharging a verify driver transistor control input is performed by coupling the verify driver transistor control input to a ground voltage.