Memory cell system with multiple nitride layers
View Patent ↗A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
1. A method for fabricating memory cells, said method comprising:
forming a charge storage stack on a semiconductor substrate by depositing a blocking oxide layer on a charge trap layer formed over a tunneling oxide layer;
nitriding a top surface of said blocking oxide layer; and
forming a semiconductor gate on said nitrided top surface of said blocking oxide layer;
wherein a silicon concentration of said charge storage stack including said tunneling oxide layer, said charge trap layer, and said blocking oxide layer is graded from a bottom surface to a top surface of said charge storage stack.
2. The method of claim 1 , further comprising:
forming a bottom blocking intermediate layer over said tunneling oxide layer and below said charge trap layer.
3. The method of claim 1 , wherein said nitriding said top surface of said blocking oxide layer results in formation of a top blocking intermediate layer on said top surface of said blocking oxide layer.
4. The method of claim 1 , wherein said nitriding said top surface of said blocking oxide layer reduces back gate injection from said semiconductor gate to said charge trap layer.
5. The method of claim 1 , wherein said nitriding said top surface of said blocking oxide layer is performed by one of slot plane antenna (SPA) plasma nitridation and decoupled plasma nitridation (DPN).
6. The method of claim 1 , wherein said formation of said charge storage stack results in a memory cell stack charging and discharging substantially by Fowler-Nordheim tunneling.
7. The method of claim 1 , further comprising:
forming a memory system from said memory cells; and
interconnecting said memory cells with a plurality of bit lines and a plurality of word lines.
8. A method for fabricating memory cells, said method comprising:
forming a charge storage stack on a semiconductor substrate by depositing a trap nitride layer on a bottom blocking intermediate layer formed over a first insulating layer;
forming a second insulating layer on said trap nitride layer;
nitriding a top surface of said second insulating layer; and
forming a semiconductor gate on said nitrided top surface of said second insulating layer;
wherein a silicon concentration of said charge storage stack including said first insulating layer, said bottom blocking intermediate layer, said trap nitride layer, and said second insulating layer is graded from a bottom surface to a top surface of said charge storage stack.
9. The method of claim 8 , wherein said bottom blocking intermediate layer is formed by nitriding a top surface of said first insulating layer or depositing a nitride on said first insulating layer.
10. The method of claim 8 , wherein said nitriding said top surface of said second insulating layer results in formation of a top blocking intermediate layer on said top surface of said second insulating layer.
11. The method of claim 8 , wherein said nitriding said top surface of said blocking oxide layer reduces back gate injection from said semiconductor gate to said charge trap layer.
12. The method of claim 8 , wherein said nitriding said top surface of said second insulating layer is performed by one of slot plane antenna (SPA) plasma nitridation and decoupled plasma nitridation (DPN).
13. The method of claim 8 , wherein said formation of said charge storage stack results in a memory cell stack charging and discharging substantially by Fowler-Nordheim tunneling.
14. The method of claim 8 , further comprising:
forming a memory system from said memory cells; and
interconnecting said memory cells with a plurality of bit lines and a plurality of word lines.
15. A memory cell comprising:
a charge storage stack disposed on a semiconductor substrate, said charge storage stack comprising:
a charge trap layer over a tunneling oxide layer;
a blocking oxide layer over said charge trap layer; and
a top blocking intermediate layer over said blocking oxide layer, said top blocking intermediate layer formed by nitriding a top portion of said blocking oxide layer; and
a semiconductor gate on said top blocking intermediate layer;
wherein a silicon concentration of said charge storage stack including said tunneling oxide layer, said charge trap layer, said blocking oxide layer, and said top blocking intermediate layer is graded from a bottom surface to a top surface of said charge storage stack.
16. The memory cell of claim 15 , further comprising:
a bottom blocking intermediate layer over said tunneling oxide layer and below said charge trap layer.
17. The memory cell of claim 15 , wherein said semiconductor gate is comprised of polysilicon.
18. The memory cell of claim 15 , wherein said charge trap layer is comprised of silicon nitride.