Dual storage node memory devices and methods for fabricating the same
View Patent ↗Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.
1. A method for fabricating a dual storage node memory device, the method comprising the steps of:
etching a plurality of trenches in a semiconductor substrate; forming a layered structure comprising a tunnel dielectric layer and a charge storage layer within the trenches;
forming a sacrificial dielectric layer overlying the layered structure;
depositing a sacrificial control gate material layer overlying the layered structure and the sacrificial dielectric layer;
etching the sacrificial control gate material layer to form plugs of the sacrificial control gate material layer within each of the plurality of trenches
forming bit lines within the semiconductor substrate;
removing the plugs of the sacrificial control gate material layer;
removing the sacrificial dielectric layer;
forming a charge barrier layer overlying the charge storage layer; and
depositing a layer of conductive material overlying the layered structure.
2. The method of claim 1 , further comprising the step of implanting impurity dopants into the layer of conductive material by ion implantation at an implant energy of about 30 keV to about 50 keV.
3. The method of claim 1 , wherein the step of etching a plurality of trenches comprises the steps of:
forming a hard mask material layer overlying the semiconductor substrate;
patterning the hard mask material layer; and
etching the semiconductor substrate to form the plurality of trenches therein.
4. The method of claim 1 , wherein the step of forming bit lines comprises the step of implanting impurity dopants into the semiconductor substrate using ion implantation.
5. The method of claim 1 wherein the step of forming a layered structure comprises the step of:
forming the tunnel dielectric layer by rapid thermal oxidation (RTO) for less than about one minute.
6. The method of claim 1 , wherein the step of forming a charge barrier layer overlying the charge storage layer comprises forming the charge barrier layer by RTO performed for less than about one minute.
7. The method of claim 3 , further comprising the steps of:
forming a dielectric liner on the semiconductor substrate;
removing the hard mask material layer; and
removing the dielectric liner.
8. A method for fabricating a semiconductor memory device, the method comprising the steps of:
etching a plurality of trenches in a semiconductor substrate;
forming a layered structure on the semiconductor substrate, wherein the layered structure comprises a tunnel dielectric layer and a charge storage layer;
forming a sacrificial dielectric layer overlying the layered structure;
depositing a sacrificial control gate material layer overlying the sacrificial dielectric layer;
removing a portion of the sacrificial control gate material layer from within the trenches;
implanting impurity dopants into the semiconductor substrate after removing the portion of the sacrificial control gate material layer;
removing the sacrificial control gate material layer;
removing the sacrificial dielectric layer;
forming a charge barrier layer overlying the charge storage layer, wherein the charge barrier layer is formed by RTO for less than about one minute; and
depositing a layer of conductive material overlying the charge barrier layer.
9. The method of claim 8 wherein the step of forming a layered structure comprises the step of:
forming the tunnel dielectric layer by rapid thermal oxidation (RTO) for less than about one minute.