IP Library Granted Patent US 8,659,175
Granted Patent B2
US 8,659,175 · App. 11/762,055 · Granted Feb 25, 2014

Integrated circuit package system with offset stack

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Quick Facts
Patent No.
US 8,659,175
App. No.
11/762,055
Granted
Feb 25, 2014
Kind
B2
Abstract

An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.

Claims (49)

1. An integrated circuit package system comprising:

a carrier;

a first integrated circuit device over the carrier;

a first internal interconnect between the carrier and the first integrated circuit device;

a second integrated circuit device having an adhesive spacer of a single layer extended from between the second integrated circuit device and the first integrated circuit device in an offset configuration from the second integrated circuit device with the first internal interconnect partially within the adhesive spacer overhanging the first integrated circuit device and extended to an outer vertical side of the second integrated circuit device;

a second internal interconnect between the carrier and the second integrated circuit device;

a package encapsulation over the first integrated circuit device, the second integrated circuit device, the first internal interconnect, and the second internal interconnect, and the second integrated circuit device over the first integrated circuit device in the offset configuration includes a connection site adjacent to a first side of the first integrated circuit device and the connection site is not being directly under the adhesive spacer; and

the second internal interconnect is connected to the second integrated circuit device at a second side of the second integrated circuit device opposite the first side.

2. The system as claimed in claim 1 further comprising a further first internal interconnect between the carrier and the first integrated circuit device includes the further first internal interconnect not within the adhesive spacer.

3. The system as claimed in claim 1 wherein:

the first integrated circuit device is a first integrated circuit die; and

the second integrated circuit device is a second integrated circuit die.

4. The system as claimed in claim 1 wherein:

the first integrated circuit device is a first integrated circuit package system; and

the second integrated circuit device is a second integrated circuit package system.

5. The system as claimed in claim 1 further comprising an external interconnect under the carrier.

6. The system as claimed in claim 1 wherein the first internal interconnect is between the carrier and the connection site.

7. The system as claimed in claim 1 wherein the second integrated circuit device having the adhesive spacer over the first integrated circuit device in the offset configuration includes the connection site adjacent to the first side of the first integrated circuit device not directly under the adhesive spacer.

8. The system as claimed in claim 1 wherein a first non-active side of the first integrated circuit device faces the carrier.

9. The system as claimed in claim 1 further comprising the first integrated circuit device and the second integrated circuit device are substantially the same size to each other.

10. A method for manufacture of an integrated circuit package system comprising:

mounting a first integrated circuit device over a carrier;

connecting a first internal interconnect between the carrier and the first integrated circuit device;

mounting a second integrated circuit device having an adhesive spacer of a single layer extended from between the second integrated circuit device and the first integrated circuit device in an offset configuration from the second integrated circuit device with the first internal interconnect partially within the adhesive spacer overhanging the first device and extended to an outer vertical side of the second integrated circuit device,

connecting a second internal interconnect between the carrier and the second integrated circuit device;

encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect, and the second integrated circuit device over the first integrated circuit device in the offset configuration includes a connection site adjacent to a first side of the first integrated circuit device and the connection site is not being directly under the adhesive spacer; and

the second internal interconnect is connected to the second integrated circuit device at a second side of the second integrated circuit device opposite the first side.

11. The method as claimed in claim 10 further comprising connecting a further first internal interconnect between the carrier and the first integrated circuit device includes connecting the further first internal interconnect not within the adhesive spacer.

12. The method as claimed in claim 10 wherein:

mounting the first integrated circuit device includes:

mounting a first integrated circuit die; and

mounting the second integrated circuit device includes:

mounting a second integrated circuit die.

13. The method as claimed in claim 10 wherein:

mounting the first integrated circuit device includes:

mounting a first integrated circuit package system; and

mounting the second integrated circuit device includes:

mounting a second integrated circuit package system.

14. The method as claimed in claim 10 further comprising attaching an external interconnect under the carrier.

15. A method for manufacture of an integrated circuit package system comprising:

mounting a first integrated circuit device over a carrier;

connecting a first internal interconnect between the carrier and the first integrated circuit device;

mounting a second integrated circuit device having an adhesive spacer of a single layer extended from between the second integrated circuit device and the first integrated circuit device in an offset configuration from the second integrated circuit device with the first internal interconnect within the adhesive spacer overhanging the first integrated circuit device and extended to an outer vertical side of the second integrated circuit device with a connection site adjacent to a first side of the first integrated circuit device not directly under the adhesive spacer;

connecting a second internal interconnect between the carrier and the second integrated circuit device at a side opposite the first side; and

encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect, and the second internal interconnect.

16. The method as claimed in claim 15 wherein connecting the first internal interconnect includes connecting the carrier and the connection site.

17. The method as claimed in claim 15 wherein mounting the second integrated circuit device having the adhesive spacer over the first integrated circuit device in the offset configuration includes exposing the connection site adjacent to the first side of the first integrated circuit device not directly under the adhesive spacer.

18. The method as claimed in claim 15 wherein mounting the first integrated circuit device includes mounting the first integrated circuit device with a first non-active side of the first integrated circuit device facing the carrier.

19. The method as claimed in claim 15 further comprising providing the first integrated circuit device and the second integrated circuit device with substantially the same size to each other.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0227. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0368 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0227 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FIRST (1ST) PAGE OF THE ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 019417 FRAME 0738. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2007
From: JU, JONG WOOK; LIM, TAEG KI; KIM, HYUN JOUNG
To: STATS CHIPPAC LTD.
Reel/Frame 019772/0241 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2007
From: JU, JONG WOOK; LIM, TAEG KI; KIM, HYUN JOUNG
To: STATS CHIPPAC LTD.
Reel/Frame 019417/0738 →