Reduced capacity carrier, transport, load port, buffer system
View Patent ↗A semiconductor workpiece processing system having at least one processing apparatus for processing workpieces, a primary transport system, a secondary transport system and one or more interfaces between first transport system and second transport system. The primary and secondary transport systems each have one or more sections of substantially constant velocity and in queue sections communicating with the constant velocity sections.
1. A semiconductor workpiece processing system comprising;
at least one processing tool for processing semiconductor workpieces;
a primary transport system having one or more constant velocity transport loops and autonomously motive carriers of semiconductor workpieces, the one or more constant velocity transport loops and the autonomously motive carriers being configured so that the autonomously motive carriers autonomously travel in a constant velocity flow along the primary transport system;
a secondary transport system having one or more constant velocity transport loops configured so that the autonomously motive carriers autonomously travel in a constant velocity flow along the secondary transport system, the secondary transport system being connected to the primary transport system through queue sections wherein, the queue sections are configured to allow the movement of autonomously motive carriers between the primary transport system and secondary transport system without disrupting the flow of either the primary or secondary transport systems;
a control unit coupled to the primary and secondary transport systems, the control unit being configured to effect movement of the autonomously motive carriers along the primary and secondary transport systems; and
one or more interfaces connected to the one or more transport loops of the secondary transport system through interface shunts for interfacing with the at least one processing tool, wherein the interface shunts are configured to allow the movement of autonomously motive carriers between the one or more transport loops of the secondary transport system and the one or more interfaces without disrupting the flow of the secondary transport system;
wherein the flow of material along the primary and secondary transport systems is continuous, and the secondary transport system and at least one of the queue sections and the interface shunts comprise a solid state motor effecting carrier travel thereon and a solid state switch effecting transitioning between the secondary transport system and at least one of the queue section and the interface shunts, the solid state switch being configured to leverage momentum of the autonomously motive carriers travelling along one of the secondary transport system, queue sections and interface shunts for effecting the transition and wherein transfer of the autonomously motive carriers onto and off of the primary and secondary transport systems is non-deterministic with respect to a transport rate of the primary and secondary transport systems.
2. A semiconductor workpiece processing system comprising:
at least one processing tool for processing semiconductor workpieces;
at least one semiconductor workpiece carrier;
a bulk transport section having a first solid state. transport system configured to drive the at least one semiconductor workpiece carrier along the bulk transport section at a substantially constant speed; and “an interface section coupled to the bulk transport section, the interface section including a second solid state transport system, the interface section being configured to interface the at least one semiconductor workpiece carrier between the bulk transport section and the at least one processing tool”; “now reads ”“an interface section coupled to the bulk transport section, the interface section including a second solid state transport system, the interface section being configured to interface the at least one semiconductor workpiece carrier between the bulk transport section and the at least one processing tool, where the interface section includes siding tracks configured to effect the substantially constant speed along the bulk transport section;
wherein the first solid state transport system and the second solid state transport system include a solid state switch for switching a transport path of the at least one semiconductor workpiece carrier between the bulk transport section and the interface section and wherein transfer of the at least one semiconductor workpiece carrier onto and off of the bulk transport section is non-deterministic with respect to a transport rate of the bulk transport section.
3. The semiconductor workpiece processing system of claim 2 , wherein the bulk transport section is configured as asynchronous transport section such that transport actions of one substrate workpiece carrier on the bulk transport section is decoupled from transport actions of other different semiconductor workpiece carriers being on the bulk transport section.
4. The semiconductor workpiece processing system of claim 3 , wherein a transport rate of the one substrate workpiece carrier is unaffected by a transport rate of the other different semiconductor workpiece carriers.
5. The semiconductor workpiece processing system of claim 2 , wherein the interface section is configured to utilize a momentum of the at least one substrate workpiece carrier for switching a path of travel of the at least one substrate workpiece carrier from the bulk transport section to the interface section.
6. The semiconductor workpiece processing system of claim 2 , wherein the bulk transport section and interface section comprise modular track segments.
7. The semiconductor workpiece processing system of claim 6 wherein the solid state switch is integrated into at least one modular track segment for switching a path of travel of the at least one semiconductor substrate carrier between the bulk transport section and interface section.
8. The semiconductor workpiece processing system of claim 2 , wherein the at least one semiconductor workpiece carrier comprises couplings for coupling the at least one semiconductor workpiece carrier with other ones of the at least one semiconductor workpiece carrier to form a carrier train.
9. The semiconductor workpiece processing system of claim 8 , wherein at least one semiconductor workpiece carrier in the carrier train is passively moved along one or ore of the bulk transport section and the interface section.