IP Library Granted Patent US 8,722,457
Granted Patent B2
US 8,722,457 · App. 11/965,383 · Granted May 13, 2014

System and apparatus for wafer level integration of components

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Quick Facts
Patent No.
US 8,722,457
App. No.
11/965,383
Granted
May 13, 2014
Kind
B2
Abstract

In a semiconductor package, a substrate has an active surface containing a plurality of active circuits. An adhesive layer is formed over the active surface of the substrate, and a known good unit (KGU) is mounted to the adhesive layer. An interconnect structure electrically connects the KGU and active circuits on the substrate. The interconnect structure includes a wire bond between a contact pad on the substrate and a contact pad on the KGU, a redistribution layer on a back surface of the substrate, opposite the active surface, a through hole via (THV) through the substrate that electrically connects the redistribution layer and wire bond, and solder bumps formed in electrical contact with the redistribution layer. The KGU includes a KGU substrate for supporting the KGU, a semiconductor die disposed over the KGU substrate, and an encapsulant formed over the semiconductor die.

Claims (77)

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer containing a plurality of first semiconductor die each having an active surface;

forming an adhesive layer on the active surface of the first semiconductor die;

providing a plurality of semiconductor packages by,

(a) providing a leadframe for each semiconductor package,

(b) mounting a second semiconductor die to a die pad on the leadframe,

(c) forming a dam around the die pad,

(d) forming a first bond wire between the second semiconductor die and a first contact pad on the leadframe, and

(e) depositing a first encapsulant in contact with the second semiconductor die and leadframe;

leading with the first encapsulant, mounting the semiconductor packages to the adhesive layer over the active surface of the first semiconductor die;

forming a second bond wire between the first contact pad on the leadframe and a contact pad on the first semiconductor die;

depositing a second encapsulant in contact with the semiconductor packages and semiconductor wafer, the dam preventing the second encapsulant from covering the die pad of the leadframe;

forming a redistribution layer over a back surface of the first semiconductor die, opposite the active surface;

forming a conductive via through the first semiconductor die to electrically connect the redistribution layer and contact pad of the first semiconductor die;

forming a first bump on the redistribution layer; and

singulating the semiconductor wafer into the individual first semiconductor die after mounting the semiconductor package, each semiconductor package being a known good unit which performs electrical functions in support of the first semiconductor die so that the active circuits in the first semiconductor die can be formed without the electrical functions performed by the semiconductor package.

2. The method of claim 1 , wherein the semiconductor package includes a quad-flat non-leaded package or ball grid array package.

3. The method of claim 1 , further including mounting a discrete semiconductor component to the first semiconductor die.

4. The method of claim 1 , further including mounting the back surface of the first semiconductor die to a printed circuit board.

5. The method of claim 1 , further including forming a second bump over a second contact pad on the leadframe.

6. The method of claim 1 , further including mounting the semiconductor package to a printed circuit board.

7. A method of making a semiconductor device, comprising:

providing a semiconductor wafer containing a plurality of first semiconductor die each having an active surface;

providing a plurality of semiconductor packages by,

(a) providing a leadframe for each semiconductor package,

(b) mounting a second semiconductor die to a die pad on the leadframe,

(c) forming a first electrical interconnection between the second semiconductor die and leadframe, and

(d) depositing a first encapsulant in contact with the second semiconductor die and leadframe;

mounting the semiconductor packages to the active surface of the first semiconductor die;

forming a second electrical interconnection between the leadframe and first semiconductor die;

depositing a second encapsulant in contact with the semiconductor packages and first semiconductor die; and

singulating the semiconductor wafer into the individual first semiconductor die after mounting the semiconductor package, each semiconductor package being a known good unit which performs electrical functions in support of the first semiconductor die so that the active circuits in the first semiconductor die can be formed without the electrical functions performed by the semiconductor package.

8. The method of claim 7 , further including:

forming a redistribution layer over a back surface of the first semiconductor die, opposite the active surface;

forming a conductive via through the first semiconductor die to electrically connect the redistribution layer and active surface of the first semiconductor die; and

forming a third electrical interconnection over the redistribution layer.

9. The method of claim 7 , further including forming a dam around the die pad to prevent the second encapsulant from covering the die pad of the leadframe.

10. The method of claim 7 , further including mounting a third semiconductor die to the first semiconductor die.

11. The method of claim 7 , further including mounting the first semiconductor die to a printed circuit board.

12. The method of claim 7 , further including mounting the semiconductor package to a printed circuit board.

13. A method of making a semiconductor device, comprising:

providing a first semiconductor die having an active surface;

providing a semiconductor package by,

(a) providing a substrate,

(b) mounting a second semiconductor die to the substrate,

(c) forming a first electrical connection between the second semiconductor die and substrate, and

(d) depositing a first encapsulant covering the second semiconductor die and substrate;

mounting the semiconductor package to the active surface of the first semiconductor die;

forming a second electrical interconnection between the substrate and first semiconductor die; and

depositing a second encapsulant covering the semiconductor package and first semiconductor die;

wherein the semiconductor package is a known good unit which performs electrical functions in support of the first semiconductor die so that the active circuits in the first semiconductor die can be formed without the electrical functions performed by the semiconductor package.

14. The method of claim 13 , further including:

forming a redistribution layer over a back surface of the first semiconductor die, opposite the active surface;

forming a conductive via through the first semiconductor die to electrically connect the redistribution layer and first semiconductor die; and

forming a third electrical interconnection over the redistribution layer.

15. The method of claim 13 , further including forming a dam around a portion of the substrate to which the second semiconductor die is mounted to prevent the second encapsulant from covering the portion of the substrate to which the second semiconductor die is mounted.

16. The method of claim 13 , further including mounting the first semiconductor die to a printed circuit board.

17. The method of claim 13 , further including mounting the semiconductor package to a printed circuit board.

18. The method of claim 13 , further including mounting a third semiconductor die to the first semiconductor die.

19. The method of claim 13 , further including mounting a third semiconductor die to the semiconductor package.

20. A method of making a semiconductor device, comprising:

providing a first semiconductor die having an active surface;

providing a semiconductor package by,

(a) providing a second semiconductor die,

(b) forming a first electrical interconnection to the second semiconductor die, and

(c) depositing a first encapsulant covering the second semiconductor die;

mounting the semiconductor package to the first semiconductor die;

forming a second electrical interconnection with the first electrical interconnection between the first semiconductor die and second semiconductor die; and

depositing a second encapsulant covering the semiconductor package and first semiconductor die;

wherein the semiconductor package is a known good unit which performs electrical functions in support of the first semiconductor die so that the active circuits in the first semiconductor die can be formed without the electrical functions performed by the semiconductor package.

21. The method of claim 20 , further including:

forming a redistribution layer over a back surface of the first semiconductor die, opposite the active surface; and

forming a conductive via through the first semiconductor die to electrically connect the redistribution layer and first semiconductor die.

22. The method of claim 20 , further including forming a dam around a portion of the substrate to which the second semiconductor die is mounted to prevent the second encapsulant from covering the portion of the substrate to which the second semiconductor die is mounted.

23. The method of claim 20 , further including mounting a third semiconductor die to the first semiconductor die.

24. The method of claim 23 , further including depositing a third encapsulant covering the third semiconductor die and first semiconductor die.

25. The method of claim 20 , further including mounting a third semiconductor die to the semiconductor package.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0227. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0368 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0227 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2007
From: CAMACHO, ZIGMUND R.; BATHAN, HENRY DESCALZO; TAY, LIONEL CHIEN HUI; MERILO, DIOSCORO A.
To: STATS CHIPPAC, LTD.
Reel/Frame 020295/0008 →