Memory address obfuscation
Apparatus, systems, and methods may operate to provide, to a memory device, an obfuscated clear-page address derived from a clear-page address that is not the same as a key-page address and/or providing, to the memory device, an obfuscated key-page address derived from the key-page address when the obfuscated clear-page address is the same as the key-page address. Additional apparatus, systems, and methods are disclosed.
1. A method, comprising:
(a) comparing a clear-page address to a key-page address, wherein a clear-page address is associated with an address for accessing a memory device without obfuscation, and a key-page address is associated with an address in memory that is used to store keys for an obfuscation scheme;
(b) responsive to the comparing of step (a) indicating the clear-page address is different from the key-page address, generating an obfuscated clear-page address by obfuscating the clear-page address;
(c) comparing the obfuscated clear-page address to the key-page address;
(d) providing, to the memory device, the obfuscated clear-page address based on the comparing of step (c) indicating that the obfuscated clear-page address is distinct from the key-page address; and
(e) based on the comparing of step (c) indicating that the obfuscated clear-page address is the same as the key-page address, generating an obfuscated key-page address by encoding the key-page address and providing the obfuscated key-page address to the memory device.
2. The method of claim 1 , further comprising:
(f) providing the clear-page address without obfuscation to the memory device when the comparing of step (a) indicates that the clear-page address is the same as the key-page address.
3. The method of claim 1 , further comprising: providing at least one of the obfuscated clear-page address and the obfuscated key-page address to the memory device comprising an array of electrically-erasable programmable read-only memory (EEPROM) cells.
4. The method of claim 1 , wherein providing, to the memory device, the obfuscated clear-page address comprises:
selecting between providing one of the clear-page address and the obfuscated clear-page address to the memory device comprising a memory address controller coupled to an array of memory storage locations.
5. The method of claim 1 , further comprising:
selecting between providing one of the clear-page address and the key-page address to a memory obfuscation module.
6. The method of claim 1 , further comprising: accessing an obfuscation key stored at the key-page address comprising a fixed address.
7. The method of claim 1 , further comprising:
determining a key-page address as a fixed address associated with a memory device comprising a nonvolatile memory;
storing one of a plurality obfuscation keys at a memory device location associated with the key-page address; and
repeating the determining and the storing for a plurality of memory devices, each having the same key-page address and a different one of the plurality of obfuscation keys.
8. The method of claim 7 , further comprising:
fabricating at least a portion of the nonvolatile memory as an array of nonvolatile memory cells, wherein some of the nonvolatile memory cells correspond to the key-page address.
9. The method of claim 8 , further comprising:
fabricating the array of nonvolatile memory cells to include at least some electrically-erasable programmable read-only memory (EEPROM) cells.
10. The method of claim 7 , wherein the key-page address may be obtained by obfuscating at least one clear-page address using an obfuscation key.
11. The method of claim 1 , wherein generating the obfuscated clear-page address by obfuscating the clear-page address further comprises:
modifying the clear-page address using the obfuscation scheme and at least one key such that the obfuscated clear-page address is distinct from the clear-page address.
12. The method of claim 1 , wherein the keys are randomly generated.
13. An apparatus, comprising:
a substrate;
an array of nonvolatile memory cells supported by the substrate; and
an address alteration module including instructions executable by a processor and operable to cause the processor to perform operations including:
comparing a clear-page address to a key-page address, wherein a clear-page address is associated with an address for accessing a memory location in the array without obfuscation, and a key-page address is associated with an address in a memory location in the array used to store keys for an obfuscation scheme;
responsive to the comparing indicating the clear-page address is different from the key-page address, generating an obfuscated clear-page address by obfuscating the clear-page address;
providing the obfuscated clear-page address to the array based on the comparing indicating that the obfuscated clear-page address is distinct from the key-page address; and
based on the comparing indicating that the obfuscated clear-page address is the same as the key-page address, generating an obfuscated key-page address by encoding the key-page address and providing the obfuscated key-page address to the array.
14. The apparatus of claim 13 , wherein the nonvolatile memory cells comprise electrically-erasable programmable read-only memory (EEPROM) cells.
15. The apparatus of claim 13 , wherein the address alteration module further comprises:
a comparator to couple to the clear-page address and the key-page address.
16. The apparatus of claim 13 , wherein the address alteration module further comprises:
a multiplexer to couple to the clear-page address and the key-page address.
17. The apparatus of claim 13 , wherein the address alteration module further comprises:
a pair of multiplexers to couple to the clear-page address, the key-page address, and an obfuscated page address derived from one of the clear-page address and the key-page address.
18. The apparatus of claim 13 , wherein the keys are randomly generated.
19. A system, comprising:
a wireless transceiver;
a processor to send data to the wireless transceiver;
a nonvolatile memory device to store the data; and
an address alteration module including instructions executable by the processor and operable to cause the processor to perform operations including:
comparing a clear-page address to a key-page address, wherein a clear-page address is associated with an address for accessing a memory location in the nonvolatile memory device without obfuscation, and a key-page address is associated with an address in the nonvolatile memory used to store keys for an obfuscation scheme;
responsive to the comparing indicating the clear-page address is different from the key-page address, generating an obfuscated clear-page address by obfuscating the clear-page address;
providing the obfuscated clear-page address to one of the nonvolatile memory device or a memory address controller coupled to the nonvolatile memory device based on the comparing indicating that the obfuscated clear-page address is distinct from the key-page address; and
based on the comparing indicating that the obfuscated clear-page address is the same as the key-page address, generating an obfuscated key-page address by encoding the key-page address and providing the obfuscated key-page address to one of the nonvolatile memory device or the memory address controller.
20. The system of claim 19 , further comprising:
a first multiplexer and a pair of comparators coupled to the key-page address.
21. The system of claim 20 , further comprising:
a second multiplexer coupled to the clear-page address, wherein the first multiplexer is also coupled to the clear-page address.
22. A non-transitory computer-readable medium having instructions stored therein for causing a computer to implement a method, comprising:
(a) comparing a clear-page address to a key-page address, wherein a clear-page address is associated with an address for accessing a memory device without obfuscation, and a key-page address is associated with an address in memory that is used to store keys for an obfuscation scheme;
(b) responsive to the comparing of step (a) indicating the clear-page address is different from the key-page address, generating an obfuscated clear-page address by obfuscating the clear-page address;
(c) comparing the obfuscated clear-page address to the key-page address;
(d) providing, to the memory device, the obfuscated clear-page address based on the comparing of step (c) indicating that the obfuscated clear-page address is distinct from the key-page address; and
(e) based on the comparing of step (c) indicating that the obfuscated clear-page address is the same as the key-page address, generating an obfuscated key-page address by encoding the key-page address and providing the obfuscated key-page address to the memory device.
23. The medium of claim 22 , wherein the method comprises:
(f) providing the clear-page address without obfuscation to the memory device when the clear-page address is the same as the key-page address.
24. The medium of claim 22 , wherein the method comprises:
(g) accessing an obfuscation key stored at a memory location associated with the key-page address, the key-page address comprising a fixed address.