IP Library Granted Patent US 9,293,350
Granted Patent B2
US 9,293,350 · App. 12/260,089 · Granted Mar 22, 2016

Semiconductor package system with cavity substrate and manufacturing method therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,293,350
App. No.
12/260,089
Granted
Mar 22, 2016
Kind
B2
Abstract

A method of manufacturing a semiconductor package system includes: providing a first substrate; providing a second substrate having a cavity, the second substrate being attached to the first substrate; connecting the first substrate to the second substrate using an interconnect, the interconnect being in the cavity; and attaching a semiconductor device to the first substrate or the second substrate.

Claims (46)

1. A method of manufacturing a semiconductor package system comprising:

providing a first substrate having a bottom side;

attaching a substrate adhesive directly to the bottom side of the first substrate;

mounting a second substrate having a top side on the bottom side of the first substrate, the top side directly facing the bottom side, the substrate adhesive directly attached between the bottom side and the top side, the second substrate having a cavity;

attaching a substrate bonding wire directly to the first substrate and the second substrate, a portion of the substrate bonding wire in the cavity;

attaching a semiconductor device directly to the bottom side of the first substrate, the semiconductor device within the cavity of the second substrate and a device sidewall of the semiconductor device facing a substrate sidewall of the second substrate;

encapsulating in a mold the semiconductor device and the second substrate, the mold in the cavity, the mold in direct contact with the second substrate only on a lower side of the second substrate and the substrate sidewall the second substrate; and

cutting the mold and the second substrate for forming a peripheral edge of the mold coplanar with a peripheral edge of the second substrate, the second substrate having the top side exposed to the peripheral edge of the second substrate.

2. The method as claimed in claim 1 wherein connecting the semiconductor device includes attaching a semiconductor die to the first substrate, the semiconductor die being in the cavity.

3. The method as claimed in claim 1 wherein connecting the semiconductor device includes attaching a first semiconductor die to the first substrate, the first semiconductor die being in the cavity, and attaching a second semiconductor die to the first semiconductor die.

4. The method as claimed in claim 1 wherein connecting the semiconductor device includes attaching a flip chip die to the first substrate, the flip chip die being in the cavity, and attaching a second semiconductor die to the flip chip die.

5. The method as claimed in claim 1 wherein connecting the semiconductor device includes attaching a discrete passive device to the second substrate.

6. A method of manufacturing a semiconductor package system comprising:

providing a first substrate having a bottom side;

attaching a substrate adhesive directly to the bottom side of the first substrate;

mounting a second substrate having a top side to the bottom side of the first substrate with a substrate adhesive on the first substrate and the second substrate, the top side directly facing the bottom side, the substrate adhesive directly attached between the bottom side and the top side, the second substrate having a cavity;

attaching a substrate bonding wire directly to the first substrate and to the second substrate, a portion of the substrate bonding wire in the cavity;

attaching a semiconductor device directly to the bottom side of the first substrate, the semiconductor device within the cavity of the second substrate and a device sidewall of the semiconductor device facing a substrate sidewall of the second substrate;

encapsulating in a mold the semiconductor device, the substrate bonding wire, and the second substrate, the mold in the cavity, the mold in direct contact with the second substrate only on a lower side of the second substrate and the substrate sidewall of the second substrate; and

cutting the mold and the second substrate for forming a peripheral edge of the mold coplanar with a peripheral edge of the second substrate, the second substrate having the top side exposed to the peripheral edge of the second substrate.

7. The method as claimed in claim 6 wherein connecting the semiconductor device includes attaching a discrete passive device to the second substrate and attaching a second type flip chip die to the second substrate through an on-chip solder ball.

8. The method as claimed in claim 6 wherein attaching the substrate bonding wire includes using a protection layer attached to the second substrate as a support layer during an interconnecting process.

9. The method as claimed in claim 6 wherein attaching the substrate bonding wire includes using a positively biased heat block attached to the second substrate as a support layer during an interconnecting process.

10. The method as claimed in claim 1 wherein encapsulating the semiconductor device, the substrate bonding wire, the second substrate, and the cavity in a mold includes using an upper mold chase and a positively biased lower mold chase.

11. A semiconductor package system comprising:

a first substrate having a bottom side;

a substrate adhesive directly attached to the bottom side of the first substrate;

a second substrate having a top side mounted to the bottom side of the first substrate, the top side directly facing the bottom side, the substrate adhesive directly attached between the bottom side and the top side, the second substrate having a cavity, the second substrate having a portion of the top side, exposed to a peripheral edge of the second substrate;

a substrate bonding wire attached directly to the first substrate and the second substrate, a portion of the substrate bonding wire in the cavity;

a semiconductor device attached to the bottom side of the first substrate, the semiconductor device within the cavity of the second substrate and a device sidewall of the semiconductor device facing a substrate sidewall of the second substrate; and

a mold encapsulating the semiconductor device and the second substrate, the mold in the cavity, the mold having a peripheral edge coplanar with the peripheral edge of the second substrate, the mold in direct contact with the second substrate only on a lower side of the second substrate and the substrate sidewall of the second substrate.

12. The system as claimed in claim 11 wherein the semiconductor device includes a semiconductor die attached to the first substrate, the semiconductor die being in the cavity.

13. The system as claimed in claim 11 wherein the semiconductor device includes a first semiconductor die attached to the first substrate, the first semiconductor die being in the cavity, and a second semiconductor die attached to the first semiconductor die.

14. The system as claimed in claim 11 wherein the semiconductor device includes a flip chip die attached to the first substrate, the flip chip die being in the cavity, and a second semiconductor die attached to the flip chip die.

15. The system as claimed in claim 11 wherein the semiconductor device includes a semiconductor die attached to the second substrate, the semiconductor die being near the cavity but not in the cavity.

16. The system as claimed in claim 11 wherein:

the mold encapsulates the substrate bonding wire.

17. The system as claimed in claim 16 wherein the semiconductor device includes a discrete passive device attached to the second substrate.

18. The system as claimed in claim 16 wherein the semiconductor device includes a discrete passive device attached to the second substrate and a second type flip chip die attached to the second substrate through an on-chip solder ball.

19. The system as claimed in claim 16 wherein the semiconductor device includes a discrete passive device attached to the second substrate and a semiconductor die attached to the second substrate.

20. The system as claimed in claim 16 further comprising:

a bottom package of a Fan-in Package-on-Package package, the bottom package having a bottom semiconductor die and a bottom interposer;

a semiconductor package attached to the bottom package as an internal stacking module;

an internal stacking module bonding wire connecting the semiconductor package system to the bottom interposer of the bottom package;

a package mold encapsulating the semiconductor package system, the bottom semiconductor die, and the internal stacking module bonding wire; and

a solder ball attached to the bottom interposer of the bottom package.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 039514 FRAME: 0451. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039980/0838 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 038378 FRAME 0442. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 039514/0451 →
CHANGE OF NAME Recorded Jul 22, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039428/0928 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0442 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2008
From: CHOW, SENG GUAN; HUANG, RUI; KUAN, HEAP HOE
To: STATS CHIPPAC LTD.
Reel/Frame 021897/0125 →