SPI addressing beyond 24-bits
View Patent ↗A system and/or methodology that facilitates serial peripheral interface (SPI) addressing beyond 24 bits, by portioning a conventional SPI command byte into a plurality of nibbles. A new set of commands are mapped to the first nibble, and selected from the set of unused binary values under the conventional SPI command protocol. A number of address bytes required to access the storage location for the command are mapped on a second nibble, and a user and/or system definable number of dummy bytes to be sent after the command are mapped on a third nibble.
1. A system that facilitates serial peripheral interface addressing, comprising:
a process coupled to at least one memory that retains instructions for:
a command byte that includes a plurality of nibbles;
a first nibble that contains a serial peripheral interface command;
a second nibble that contains a value related to a number of address bytes needed to access a memory location for the serial peripheral interface command; and
a third nibble that contains a number of dummy bytes to be sent after the command, the dummy bytes determine the number of wait states to be performed after the command.
2. The system of claim 1 , the command byte is comprised of 8 bits, the first nibble is 4 bits, the second nibble is 2 bits, and the third nibble is 2 bits.
3. The system of claim 2 , the serial peripheral interface command contained in the first nibble is at least one of a multi-byte read, multi-byte write, or multi-byte erase command.
4. The system of claim 3 , the serial peripheral interface command for a multi-byte erase is a 6 or 0110 in binary form, multi-byte is a 7 or 0111 in binary form, and multi-byte write is a 8 or 1000 in binary form.
5. The system of claim 1 , the serial peripheral interface commands in the first nibble are unassigned binary values in a standard serial peripheral interface addressing protocol, wherein the unassigned binary values do not conflict with standard serial peripheral interface protocol commands.
6. The system of claim 1 , the value contained in the second nibble is three less than the number of address bytes needed to access a memory location to perform the serial peripheral interface command.
7. A method of facilitating serial peripheral interface addressing, comprising:
partitioning a command byte into a plurality of nibbles;
encoding a command onto a first nibble;
encoding a second nibble to contain a number of address bytes necessary to access a memory location for the command; and
encoding a quantity of dummy bits to be sent after the command in a third nibble; and
mapping the commands in the first nibble to unassigned binary values in a standard serial peripheral interface addressing protocol, wherein the unassigned binary values do not conflict with standard serial peripheral interface protocol commands.
8. The method of claim 7 , allocating 4 bits to the first nibble, 2 bits to the second nibble, and the 2 bits to the third nibble, wherein the command byte is comprised of 8 bits.
9. The method of claim 8 , further comprising encoding the command contained in the first nibble to include at least one of a multi-byte read, multi-byte write, or multi-byte erase command.
10. The method of claim 9 , further comprising setting the command for a multi-byte erase as a 6 or 0110 in binary form, for a multi-byte read as a 7 or 0111 in binary form, and for a multi-byte write as a 8 or 1000 in binary form.
11. The method of claim 7 , further comprising setting the value contained in the second nibble to be three less than the number of address bytes needed to access a memory location to perform the command.
12. The method of claim 7 , further comprising determining a number of wait states to be performed after the command based on the number dummy bytes.
13. A method of facilitating serial peripheral interface addressing, comprising:
obtaining a command byte;
analyzing a first nibble in the command byte to determine a command;
analyzing a second nibble in the command byte to determine a number of address bytes required to access a storage location for execution of the command; and
analyzing a third nibble in the command to determine a number of dummy bytes to be sent after the command; and
analyzing the first 4 bits of the command byte to determine first nibble, the following 2 bits to determine the second nibble, and the following 2 bits to determine the third nibble, wherein the command byte is comprised of 8 bits.
14. The method of claim 13 , further comprising determining the command is a multi-byte erase if the first nibble contains a 6 or 0110 in binary form, a multi-byte read if the first nibble contains a 7 or 0111 in binary form, or a multi-byte write if the first nibble contains an 8 or 1000 in binary form.
15. The method of claim 13 , further comprising adding three to the value contained in the second nibble to determine the number of address bytes following the command byte to access a memory location for the command.
16. The method of claim 13 , further comprising determining a number of wait states to be performed after the command based on the number of dummy bytes.