IP Library Granted Patent US 8,493,491
Granted Patent B2
US 8,493,491 · App. 12/967,311 · Granted Jul 23, 2013

Methods for processing an image captured by an image sensor having multiple output channels

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Quick Facts
Patent No.
US 8,493,491
App. No.
12/967,311
Granted
Jul 23, 2013
Kind
B2
Abstract

Charge packets are transferred from a pixel array in an image sensor to a horizontal shift register. Each charge packet is shifted to a non-destructive sense node. Each charge packet is non-destructively sensed and a signal representative of a number of charge carriers in the charge packet is produced. Respective charge packets are directed to a charge multiplying output channel when the signal representative of the number of charge carriers in each charge packet indicates the charge packet will not saturate the charge multiplying horizontal shift register. Respective charge packets are directed to a charge bypass output channel or an amplifier when the signal representative of the number of charge carriers in each charge packet indicates the charge packet will saturate the charge multiplying horizontal shift register.

Claims (16)

1. A method for processing an image captured by a pixel array in an image sensor, the method comprising:

transferring charge packets from the pixel array to a horizontal shift register;

shifting each charge packet to a non-destructive sense node;

non-destructively sensing each charge packet and producing a signal representative of a number of charge carriers in the charge packet; and

for each charge packet:

if the signal representative of the number of charge carriers in the charge packet indicates the charge packet will not saturate a charge multiplying horizontal shift register configured to accept charge packets from the horizontal shift register and multiply the number of charge carriers in the charge packet, directing the entire charge packet to the charge multiplying horizontal shift register, and

if the signal representative of the number of charge carriers in the charge packet indicates the charge packet will saturate the charge multiplying horizontal shift register, either (i) directing the entire charge packet to bypass the charge multiplying horizontal shift register and enter a charge bypass horizontal shift register configured to accept charge packets from the horizontal shift register and shift charge packets without charge multiplication, or (ii) directing the entire charge packet to bypass the charge multiplying horizontal shift register and enter an amplifier configured to accept charge packets from the horizontal shift register and output a signal representing the number of charge carriers in the charge packet.

2. The method as in claim 1 , wherein the charge packet is directed to the charge bypass horizontal shift register when the signal representative of the number of charge carriers in the charge packet indicates the charge packet will saturate the charge multiplying horizontal shift register.

3. The method as in claim 2 , wherein a charge multiplying output channel connected to an output of the charge multiplying horizontal shift register has an associated charge to voltage conversion gain value G 3 and a charge bypass output channel connected to an output of the charge bypass horizontal shift register has an associated charge to voltage conversion gain value G 2 .

4. The method as in claim 3 , further comprising applying a gain ratio of G 3 /G 2 to each pixel signal produced by the charge bypass output channel.

5. The method as in claim 2 , wherein directing the charge packet to the charge bypass horizontal shift register when the signal representative of the number of charge carriers in the charge packet indicates the charge packet will saturate the charge multiplying horizontal shift register comprises configuring a charge directing switch to direct the charge packet to the charge bypass horizontal shift register when the signal representative of the number of charge carriers in the charge packet indicates the charge packet will not saturate the charge multiplying horizontal shift register.

6. The method as in claim 1 , wherein the charge packet is directed to the amplifier when the signal representative of the number of charge carriers in the charge packet indicates the charge packet will saturate the charge multiplying horizontal shift register.

7. The method as in claim 6 , wherein directing the charge packet to the amplifier when the signal representative of the number of charge carriers in the charge packet indicates the charge packet will saturate the charge multiplying horizontal shift register comprises configuring a charge directing switch to direct the charge packet to the amplifier when the signal representative of the number of charge carriers in the charge packet indicates the charge packet will saturate the charge multiplying horizontal shift register.

8. The method as in claim 1 , wherein (i) the sense node is connected to a charge sensing output channel having an associated charge to voltage conversion gain value G 1 and (ii) a charge multiplying output channel connected to an output of the charge multiplying horizontal shift register has an associated charge to voltage conversion gain value G 3 .

9. The method as in claim 8 , further comprising applying a gain ratio of G 3 /G 1 to each pixel signal produced by the charge sensing output channel.

10. The method as in claim 1 , wherein directing the charge packet to the charge multiplying horizontal shift register when the signal representative of the number of charge carriers in the charge packet indicates the charge packet will not saturate the charge multiplying horizontal shift register comprises configuring a charge directing switch to direct the charge packet to the charge multiplying horizontal shift register when the signal representative of the number of charge carriers in the charge packet indicates the charge packet will not saturate the charge multiplying horizontal shift register.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 22, 2015
From: TRUESENSE IMAGING, INC
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 036656/0412 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2014
From: TRUESENSE IMAGING, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033460/0457 →
TERMINATION AND RELEASE OF PATENT SECURITY AGREEMENT Recorded May 19, 2014
From: PNC BANK, NATIONAL ASSOCIATION
To: TRUESENSE IMAGING, INC.
Reel/Frame 032936/0167 →
CHANGE OF NAME Recorded Dec 29, 2011
From: IMAGE SENSOR TECHNOLOGIES ACQUISITION CORPORATION
To: TRUESENSE IMAGING, INC.
Reel/Frame 027463/0523 →
SECURITY AGREEMENT Recorded Dec 9, 2011
From: TRUESENSE IMAGING, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 027354/0722 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2011
From: EASTMAN KODAK COMPANY
To: IMAGE SENSOR TECHNOLOGIES ACQUISITION CORPORATION
Reel/Frame 027328/0892 →