IP Library Granted Patent US 9,017,540
Granted Patent B2
US 9,017,540 · App. 13/162,408 · Granted Apr 28, 2015

Systems and methods for reducing overhang on electroplated surfaces of printed circuit boards

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Quick Facts
Patent No.
US 9,017,540
App. No.
13/162,408
Granted
Apr 28, 2015
Kind
B2
Abstract

Systems and methods for reducing overhang on electroplated surfaces of printed circuit boards are described. One such method includes applying a first resist layer on a substrate having a first copper layer, applying a first image to the first resist layer, developing the first resist layer in accordance with the first image, applying a second copper layer on the first copper layer, electroplating a first metallic layer on the second copper layer, removing the first resist layer, etching a portion of the first copper layer, removing the first metallic layer, depositing a third copper layer on a surface of the assembly, applying a second resist layer on the third copper layer, applying a second image to the second resist layer, developing the second resist layer in accordance with the second image, electroplating a preselected metal layer on the third copper layer, removing the second resist layer, and etching a portion of the third copper layer.

Claims (32)

1. A method for manufacturing a printed circuit board assembly, the method comprising:

applying a first resist layer on at least one part of a substrate having a first copper layer formed on a first surface of the substrate;

applying a first image to at least one part of the first resist layer;

developing the first resist layer in accordance with the first image;

applying a second copper layer on a surface of the first copper layer;

electroplating a first metallic layer on at least a portion of a surface of the second copper layer;

removing the first resist layer;

etching at least a portion of the first copper layer;

removing the first metallic layer;

depositing a third copper layer that contacts and covers at least a portion of the second copper layer, at least a portion of the first copper layer, and at least as portion of the substrate of the printed circuit board assembly;

applying a second resist layer on the third copper layer;

applying a second image to at least one part of the second resist layer;

developing the second resist layer in accordance with the second image;

electroplating a preselected metal layer on at least a portion of the third copper layer;

removing the second resist layer; and

etching the third copper layer from at least a portion of the second copper layer not covered by the preselected metal layer, the at least a portion of the first copper layer, and the at least portion of the substrate.

2. The method of claim 1 , wherein the electroplating the preselected metal layer on the at least the portion of the third copper layer comprises:

electroplating a nickel layer on at least a portion of the third copper layer; and

electroplating a gold layer on the nickel layer.

3. The method of claim 1 , wherein the first metallic layer comprises tin.

4. The method of claim 1 , wherein the first metallic layer comprises tin and lead.

5. The method of claim 1 , wherein the applying the second image to the at least one part of the second resist layer comprises aligning the second image along the second resist layer in accordance with a location of the first image.

6. The method of claim 5 , wherein the aligning the second image along the second resist layer in accordance with the location of the first image comprises at least some mis-alignment between a location of the second image and the location of the first image.

7. The method of claim 1 , wherein a width of the second image is less than a width of the first image.

8. The method of claim 1 , wherein a width of the second image is greater than a width of the first image.

9. The method of claim 1 , wherein the developing the second resist layer in accordance with the second image comprises sanding the second resist layer in accordance with the second image.

10. The method of claim 1 , wherein the first resist layer comprises a resist selected from the group consisting of a liquid photoresist, a dry film resist, a positive photoresist, and a negative photoresist.

11. The method of claim 1 , wherein the applying a second resist layer on the third copper layer comprises using a process selected from the group consisting of an ink jet process, a screen print process, a spray coat process, a roller coat process, a dip coat process, a roll laminate process, and an electroplating process.

12. The method of claim 1 , wherein the electroplating the preselected metal layer on the at least a portion of the third copper layer comprises wrapping at least a portion of the preselected metal layer along a side wall formed by the first copper layer and the second copper layer.

13. The method of claim 1 , wherein the etching the at least the portion of the third copper layer comprises using a copper etching solution selected from the group consisting of ammoniacal etch, persulfate etch, and sulfuric peroxide etch.

14. The method of claim 1 , wherein the depositing the third copper layer on the surface of the printed circuit board assembly comprises using a deposition process selected from the group consisting of electroless deposition, sputter deposition, spray coating deposition, and chemical vapor deposition.

15. The method of claim 1 , wherein a width of the second image is about equal to a width of the first image.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (035858/0890) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TTM TECHNOLOGIES, INC. (FORMERLY KNOWN AS VIASYSTEMS GROUP, INC. AND VIASYSTEMS, INC.); TTM TECHNOLOGIES NORTH AMERICA, LLC (FORMERLY KNOWN AS VIASYSTEMS TECHNOLOGIES CORP., L.L.C.)
Reel/Frame 075681/0922 →
CHANGE OF NAME Recorded May 12, 2023
From: VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
To: TTM TECHNOLOGIES NORTH AMERICA, INC.
Reel/Frame 063635/0226 →
PATENT SECURITY AGREEMENT-ABL Recorded Jun 8, 2015
From: TTM TECHNOLOGIES, INC.; VIASYSTEMS, INC.; VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 035858/0890 →
PATENT SECURITY AGREEMENT-TERM Recorded Jun 8, 2015
From: TTM TECHNOLOGIES, INC.; VIASYSTEMS, INC.; VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 035851/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2014
From: VIASYSTEMS NORTH AMERICA OPERATIONS, INC.
To: VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
Reel/Frame 031937/0500 →
CHANGE OF NAME Recorded Dec 31, 2013
From: DDI GLOBAL CORP.
To: VIASYSTEMS NORTH AMERICA OPERATIONS, INC.
Reel/Frame 031863/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2011
From: SIDHU, RAJWANT S.; ZEPEDA, RUBEN; LOPEZ, CARLOS A.
To: DDI GLOBAL CORPORATION
Reel/Frame 026810/0785 →