IP Library › Granted Patent US 8,829,883
Granted Patent B2
US 8,829,883 · App. 13/228,972 · Granted Sep 9, 2014

Leakage-current compensation for a voltage regulator

Inventor: Lourans Samid (Heilbronn, DE)
Assignee: Atmel Corporation
G05F1/56
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Quick Facts
Patent No.
US 8,829,883
App. No.
13/228,972
Granted
Sep 9, 2014
Kind
B2
Abstract

In one embodiment, a method includes generating a drive current. Generation of the drive current results in a first leakage current, and the drive current and first leakage current each flow into a first node. The method also includes generating a second leakage current and amplifying the second leakage current to generate a leakage-compensation current. The leakage-compensation current flows away from the first node.

Claims (42)

1. A circuit comprising:

a first transistor coupled to a first node, the first transistor configured to generate a drive current, generation of the drive current resulting in a first leakage current from the first transistor, the drive current and the first leakage current each flowing when generated into the first node; and

a first leakage-current compensation circuit coupled to the first node and comprising:

a second transistor configured to generate a second leakage current; and

a first current mirror comprising a third transistor and a fourth transistor, the first current mirror configured to receive and amplify the second leakage current to generate a leakage-compensation current, the leakage-compensation current flowing when generated away from the first node and through the fourth transistor of the first current mirror;

wherein the first transistor and a fifth transistor comprise a second current mirror.

2. The circuit of claim 1 , wherein an amount of the drive current generated by the first transistor is based on a difference between a reference voltage and a fraction of a voltage at the first node.

3. The circuit of claim 1 , wherein:

the second transistor comprises a p-type metal oxide semiconductor field-effect transistor (MOSFET);

a gate and a source of the second transistor are coupled to a supply voltage of the circuit; and

a drain of the second transistor is coupled to the first current mirror.

4. The circuit of claim 1 , wherein the second current mirror is configured to receive and amplify a current generated by a differential amplifier according to a difference between a reference voltage and a fraction of a voltage at the first node.

5. The circuit of claim 4 , wherein an aspect ratio of the second transistor is approximately equal to an aspect ratio of the fifth transistor.

6. The circuit of claim 5 , wherein an aspect ratio of the fourth transistor divided by an aspect ratio of the third transistor is approximately equal to an aspect ratio of the first transistor divided by the aspect ratio of the fifth transistor.

7. A method comprising:

generating, by a first transistor coupled to a first node, a drive current, generation of the drive current resulting in a first leakage current from the first transistor, the drive current and first leakage current each flowing into the first node;

generating, by a second transistor in a leakage-current compensation circuit coupled to the first node, a second leakage current; and

amplifying, by a first current mirror in the leakage-current compensation circuit, the second leakage current to generate a leakage-compensation current, the leakage-compensation current flowing away from the first node, the leakage-current compensation circuit comprising a third transistor and a fourth transistor, the first transistor and a fifth transistor comprising a second current mirror.

8. The method of claim 7 , wherein an amount of the drive current is based on a difference between a reference voltage and a fraction of a voltage at the first node.

9. The method of claim 7 , wherein:

the second transistor comprises a p-type metal oxide semiconductor field-effect transistor (MOSFET);

a gate and a source of the second transistor are coupled to a supply voltage; and

a drain of the second transistor is coupled to the first current mirror.

10. The method of claim 7 , further comprising the second current mirror amplifying a current generated by a differential amplifier according to a difference between a reference voltage and a fraction of a voltage at the first node.

11. The method of claim 7 , wherein an aspect ratio of the second transistor is approximately equal to an aspect ratio of the fifth transistor.

12. The method of claim 11 , wherein an aspect ratio of the fourth transistor divided by an aspect ratio of the third transistor is approximately equal to an aspect ratio of the first transistor divided by the aspect ratio of the fifth transistor.

13. A transceiver comprising:

a circuit comprising:

a first transistor coupled to a first node, the first transistor configured to generate a drive current, generation of the drive current resulting in a first leakage current from the first transistor, the drive current and the first leakage current each flowing when generated into the first node; and

a leakage-current compensation circuit coupled to the first node and comprising:

a second transistor configured to generate a second leakage current; and

a first current mirror comprising a third transistor and a fourth transistor, the first current mirror configured to receive and amplify the second leakage current to generate a leakage-compensation current, the leakage-compensation current flowing when generated away from the first node and through the fourth transistor of the first current mirror;

a transmitter configured to use at least a first portion of the drive current while transmitting data; and

a receiver configured to use at least a second portion of the drive current while receiving data;

wherein the first transistor and a fifth transistor comprise a second current mirror.

14. The transceiver of claim 13 , wherein the transmitter and receiver are coupled to a local interconnect network (LIN).

15. The transceiver of claim 13 , wherein the transmitter and receiver are coupled to a local interconnect network (LIN) of an automobile.

16. The transceiver of claim 13 , wherein an amount of drive current generated by the first transistor is based on a difference between a reference voltage and a fraction of a voltage at the first node.

17. The transceiver of claim 13 , wherein:

the second transistor comprises a p-type metal oxide semiconductor field-effect transistor (MOSFET);

a gate and a source of the second transistor are coupled to a supply voltage of the circuit; and

a drain of the second transistor is coupled to the first current mirror.

Assignments (18)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2011
From: ATMEL AUTOMOTIVE GMBH
To: ATMEL CORPORATION
Reel/Frame 026975/0425 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2011
From: SAMID, LOURANS
To: ATMEL AUTOMOTIVE GMBH
Reel/Frame 026881/0248 →
Continuity (1)
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