Granted Patent B2

US 8,536,907 · App. 13/244,279 · Granted Sep 17, 2013

Abstract

Claims (25)

1. A power on reset signal generating apparatus, comprising:

a trigger capacitor, one end of the trigger capacitor coupled to a ground voltage, the other end of the trigger capacitor coupled to a signal generating end, a power on reset signal is generated at the signal generating end;

a reference current supplying circuit, coupled to the signal generating end, and the reference current applying circuit supplying a reference current to the signal generating end, wherein the reference current supplying circuit comprises:

a current source, comprises at least a transistor;

a first current mirror, an input terminal of the first current mirror coupled to the current source, and the first current mirror mirroring the current supplied by the current source to generate a first current at the end of an output terminal of the current mirror; and

a second current mirror, coupled to the first current mirror, and the second current mirror receiving and mirroring the first current to generate the reference current,

wherein, the drain end of the transistor and the source end of the transistor are connected to a power voltage and the first current mirror respectively, and the gate end of the transistor is coupled to the ground voltage; and

a current regulator, coupled to the signal generating end, and a splitting current flowing from the signal generating end into the current regulator for adjusting the value of the current received by the trigger capacitor.

2. The power on reset signal generating apparatus as claimed in claim 1 , wherein the first current mirror comprises:

a first transistor, the drain end of the first transistor coupled to the current source, the gate end of the first transistor coupled to the drain end of the first transistor, and the source end of the first transistor coupled to the ground voltage; and

a second transistor, the drain end of the second transistor coupled to the second current mirror, the gate end of the second transistor coupled to the gate end of the first transistor, and the source end of the second transistor coupled to the ground voltage.

3. The power on reset signal generating apparatus as claimed in claim 2 , wherein the second current mirror comprises:

a third transistor, the drain end of the third transistor coupled to the drain end of the second transistor, the gate end of the third transistor coupled to the drain end of the third transistor, and the source end of the third transistor coupled to a power voltage;

a fourth transistor, the drain end of the fourth transistor coupled to the current regulator, the gate end of the fourth transistor coupled to the gate end of the third transistor, and the source end of the fourth transistor coupled to the power voltage; and

a fifth transistor, the drain end of the fifth transistor coupled to the trigger capacitor, the gate end of the fifth transistor coupled to the gate end of the third transistor, and the source end of the fifth transistor coupled to the power voltage.

4. The power on reset signal generating apparatus as claimed in claim 3 , wherein the current regulator comprises a third current minor and the third current mirror comprises:

a sixth transistor, the drain end of the sixth transistor coupled to the drain end of the fourth transistor, the gate end of the sixth transistor coupled to the drain end of the sixth transistor, and the source end of the sixth transistor coupled to the ground voltage; and

a seventh transistor, the drain end of the seventh transistor coupled to the trigger capacitor, the gate end of the seventh transistor coupled to the gate end of the sixth transistor, and the source end of the seventh transistor coupled to the ground voltage.

5. The power on reset signal generating apparatus as claimed in claim 2 , wherein the first transistor and the second transistor are N-type transistors.

6. The power on reset signal generating apparatus as claimed in claim 3 , wherein the third transistor, the fourth transistor and the fifth transistor are P-type transistors.

7. The power on reset signal generating apparatus as claimed in claim 4 , wherein the sixth transistor and the seventh transistor are N-type transistors.

8. The power on reset signal generating apparatus as claimed in claim 1 , further comprising:

a voltage trigger, coupled to the signal generating end, and generating an adjusted power on reset signal according to the power on reset signal.

9. The power on reset signal generating apparatus as claimed in claim 8 , further comprising:

a buffer, coupled to the voltage trigger, receiving the adjusted power on reset signal ,and generating a buffer power on reset signal.

Assignments (18)