Using bump bonding to distribute current flow on a semiconductor power device
A semiconductor power chip may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; a plurality of ball bumps or a loaf bump disposed on each of the plurality of second elements and the plurality of third elements; and at least one ball bump or loaf on the at least one first contact element.
1. A semiconductor power chip, comprising:
a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device comprises at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of said semiconductor die, wherein the first, second and third contact elements are arranged in parallel and each has the form of an elongated strip;
a loaf bump disposed on each of the plurality of second contact elements and the plurality of third contact elements wherein each loaf bump extends substantially over a respective surface area of the plurality of second contact elements and the plurality of third contact elements; and
at least one ball bump or loaf on the at least one first contact element.
2. A semiconductor power chip according to claim 1 , wherein the first contact element is a gate contact element, the second contact element is a source contact element, and the third contact element is a drain contact element.
3. A semiconductor power chip according to claim 1 , wherein each elongated strip substantially extends between two opposing sides of the semiconductor die.
4. A semiconductor power chip according to claim 1 , further comprising a plurality of first contact elements wherein each first contact element comprises a plurality of ball bumps.
5. A semiconductor power chip according to claim 1 , further comprising a plurality of first contact elements wherein each first contact element comprises a loaf bump extending substantially along the first contact element.
6. A semiconductor power device, comprising a semiconductor power chip according to claim 2 , further comprising:
a lead-frame having an area comprising gate, source and drain lead-fingers adapted to match up with the plurality of ball bumps or the loaf bump for connecting to each of the at least one gate contact element, the plurality of source contact elements and the plurality of drain contact elements.
7. The semiconductor power device according to claim 6 , wherein each lead finger has the form of an elongated strip.
8. The semiconductor power device according to claim 7 , wherein the leadframe further comprises left and right connection elements that interconnect the drain and source lead fingers, respectively.
9. The semiconductor power device according to claim 8 , wherein the drain and source lead fingers are arranged alternatively to form a inter-digital structure.
10. The semiconductor power device according to claim 6 , further comprising a plurality of ball bumps disposed on the at least one gate contact element.
11. The semiconductor power device according to claim 6 , further comprising a loaf bump disposed on the at least one gate contact element.
12. A semiconductor power device, comprising at least a first and second semiconductor power chip, each semiconductor power chip being formed according to claim 2 , further comprising:
a lead-frame having an first and second area each first and second area comprising gate, source and drain lead-fingers adapted to match up with the plurality of ball bumps or the loaf bump for connecting to each of the at least one gate contact element, the plurality of source contact elements and the plurality of drain contact elements of said first and second semiconductor chips, respectively.
13. The semiconductor power device according to claim 12 , wherein each lead finger has the form of an elongated strip.
14. The semiconductor power device according to claim 12 , wherein the leadframe further comprises left and right connection elements for each of said first and second power semiconductor chips that interconnect the drain and source lead fingers, respectively.
15. The semiconductor power device according to claim 14 , wherein the drain and source lead fingers are arranged alternatively to form a inter-digital structure.
16. The semiconductor power device according claim 12 , wherein the lead-frame also connects together a source of said first semiconductor chip and a drain of said second semiconductor chip.
17. The semiconductor power device according to claim 12 , further comprising a plurality of ball bumps disposed on the at least one gate contact element.
18. The semiconductor power device according to claim 12 , further comprising a loaf bump disposed on the at least one gate contact element.
19. A semiconductor device comprising a semiconductor power chip according to claim 2 , further comprising:
another chip;
a lead-frame having a first area comprising gate, source and drain lead-fingers adapted to match up with the plurality of ball bumps or loaf bumps for connecting to each of the at least one gate contact element, the plurality of source contact elements and the plurality of drain contact elements of the semiconductor power chip and a second area configured for wire bonding said another chip.
20. The semiconductor power device according to claim 19 , wherein each lead finger has the form of an elongated strip.
21. The semiconductor power device according to claim 20 , wherein the leadframe further comprises left and right connection elements that interconnect the drain and source lead fingers, respectively.
22. The semiconductor power device according to claim 21 , wherein the drain and source lead fingers are arranged alternatively to form a inter-digital structure.
23. The semiconductor device according to claim 19 , further comprising a plurality of ball bumps or a loaf bump disposed on the at least one gate contact element.
24. The semiconductor device according to claim 19 , wherein the another chip is a microcontroller chip operable to control said semiconductor power chip.
25. The semiconductor device according to claim 19 , wherein the another chip is a pulse width modulation chip operable to control said semiconductor power chip.
26. A semiconductor device comprising at least a first and second semiconductor power chip, each semiconductor power chip being formed according to claim 2 , further comprising:
a third chip;
a lead-frame having an first and second area each first and second area comprising gate, source and drain lead-fingers adapted to match up with the plurality of ball bumps or the loaf bumps for connecting to each of the at least one gate contact element, the plurality of source contact elements and the plurality of drain contact elements of said first and second semiconductor chips, respectively and a third area configured for wire bonding said another chip.
27. The semiconductor power device according to claim 26 , wherein each lead finger for said first and second semiconductor power chip has the form of an elongated strip.
28. The semiconductor power device according to claim 27 , wherein the leadframe further comprises for each of said first and second semiconductor power chips left and right connection elements that interconnect the drain and source lead fingers, respectively.
29. The semiconductor power device according to claim 28 , wherein the drain and source lead fingers are arranged alternatively to form a inter-digital structure.
30. The semiconductor device according to claim 26 , further comprising a plurality of ball bumps or a loaf bump disposed on the at least one gate contact element.
31. The semiconductor device according to claim 26 , wherein the third chip is a microcontroller chip operable to control said semiconductor power chip.
32. The semiconductor device according to claim 26 , wherein the third chip is a pulse width modulation chip operable to control said semiconductor power chip.
33. A semiconductor power chip, comprising:
a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device comprises at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of said semiconductor die, wherein the first, second and third contact elements are arranged in parallel and each has the form of an elongated strip;
a plurality of loaf bumps, each loaf bump disposed on one of the plurality of second elements and on one of the plurality of third elements; wherein the loaf bumps for the second contact elements extend towards one side of the semiconductor die and are joined by a first loaf side structure and the loaf bumps for the third contact elements extend towards the other side of the semiconductor die and are joined by a second loaf side structure;
at least one ball bump or loaf on the at least one first contact element.
34. A semiconductor power chip according to claim 33 , wherein the first contact element is a gate contact element, the second contact element is a source contact element, and the third contact element is a drain contact element.
35. A semiconductor power device, comprising a semiconductor power chip according to claim 33 , further comprising:
a lead-frame having a first area for contact with the first contact element, a second area for contact with the first loaf side structure and a third area for contact with the second loaf side structure.
36. A semiconductor power device, comprising a semiconductor power chip according to claim 35 , wherein the leadframe does not substantially cover the second and third contact elements.
37. A semiconductor power chip according to claim 33 , wherein each elongated strip substantially extends between two opposing sides of the semiconductor die.