Integrated circuit packaging system with coupling features and method of manufacture thereof
View Patent ↗A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature.
1. A method of manufacture of an integrated circuit packaging system comprising:
providing a wafer substrate having an active side containing a contact;
forming a through silicon via extending through the wafer substrate electrically coupled to the contact having a via width;
forming a first coupling feature, on the through silicon via, extending from the active side;
forming a second coupling feature on the side of the through silicon via opposite the first coupling feature; and
forming a conductive adhesive cap directly on the second coupling feature, wherein forming the first coupling feature includes the first coupling feature having a first coupling feature diameter smaller than a second coupling feature diameter.
2. The method as claimed in claim 1 wherein forming the first coupling feature includes forming a via post or a via hole.
3. The method as claimed in claim 1 wherein forming the second coupling feature includes forming a via post or a via hole.
4. The method as claimed in claim 1 further comprising:
forming a first insulation layer directly on the contact and the wafer substrate;
forming a second insulation layer directly on the first insulation layer;
forming a contact opening through the first insulation layer and the second insulation layer exposing the contact; and
forming a metal layer directly on the second insulation layer and the contact.
5. The method as claimed in claim 4 wherein forming the second coupling feature includes removing a portion of the second insulation layer covering the second coupling feature.
6. The method as claimed in claim 1 further comprising:
forming a via recess by etching the wafer substrate; and
forming a via rim recess along an outer circumference of the via recess with a deposit mask having a diameter less than a via width.
7. The method as claimed in claim 6 wherein forming the second coupling feature includes removing a portion of the wafer substrate for exposing the second coupling feature.
8. The method as claimed in claim 1 wherein forming the second coupling feature includes forming a barrier layer directly on the second coupling feature for preventing diffusion between the through silicon via and the conductive adhesive cap.
9. An integrated circuit packaging system comprising:
a wafer substrate having an active side;
a contact formed directly on the wafer substrate;
a through silicon via extending through the wafer substrate electrically connected to the contact and having a via width;
a first coupling feature extending from a top side of the through silicon via; and
a second coupling feature on the side of the through silicon via opposite the first coupling feature;
a conductive adhesive cap directly on the second coupling feature;
the first coupling feature includes a first coupling feature diameter; and
the second coupling feature includes a second coupling feature diameter larger than the first coupling feature diameter.
10. The system as claimed in claim 9 wherein the first coupling feature includes a via post or a via hole.
11. The system as claimed in claim 9 wherein the second coupling feature is a via post or a via hole.
12. The system as claimed in claim 9 further comprising:
a first insulation layer directly on the contact and the wafer substrate having a contact opening over the contact;
a second insulation layer directly on the first insulation layer having a contact opening over the contact; and
a metal layer directly on the second insulation layer and the contact.
13. The system as claimed in claim 12 wherein the second coupling feature is exposed from the second insulation layer.
14. The system as claimed in claim 9 wherein the wafer substrate includes:
the wafer substrate having a via recess extending through the wafer substrate; and
the wafer substrate having a via rim recess along an outer circumference of the via recess.
15. The system as claimed in claim 14 wherein the second coupling feature is exposed from the wafer substrate.
16. An integrated circuit packaging system comprising:
a wafer substrate having an active side;
a contact formed directly on the wafer substrate;
a through silicon via extending through the wafer substrate electrically connected to the contact and having a via width;
a first coupling feature extending from a top side of the through silicon via; and
a second coupling feature on the side of the through silicon via opposite the first coupling feature; and
a conductive adhesive cap directly on the second coupling feature, wherein the second coupling feature includes a barrier layer directly on the second coupling feature for preventing diffusion between the through silicon via and the conductive adhesive cap.
17. The system as claimed in claim 16 wherein the first coupling feature includes a via post or a via hole.
18. The system as claimed in claim 16 wherein the second coupling feature is a via post or a via hole.
19. The system as claimed in claim 16 further comprising:
a first insulation layer directly on the contact and the wafer substrate having a contact opening over the contact;
a second insulation layer directly on the first insulation layer having a contact opening over the contact; and
a metal layer directly on the second insulation layer and the contact.
20. The system as claimed in claim 16 wherein the wafer substrate includes:
the wafer substrate having a via recess extending through the wafer substrate; and
the wafer substrate having a via rim recess along an outer circumference of the via recess.