Semiconductor device and method of forming FO-WLCSP with multiple encapsulants
View Patent ↗A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.
1. A method of making a semiconductor device, comprising:
providing a carrier with a thermally releasable layer;
mounting a first semiconductor die including through silicon vias (TSVs) to the thermally releasable layer;
depositing a first encapsulant having a first coefficient of thermal expansion (CTE) over the first semiconductor die;
exposing a surface of the TSVs;
mounting a second semiconductor die to the surface of the TSVs;
depositing a second encapsulant having a second CTE over the first semiconductor die and second semiconductor die; and
forming an interconnect structure over the first and second semiconductor die.
2. The method of claim 1 , further including forming the first and second encapsulants over and around the first and second semiconductor die with a chase mold.
3. The method of claim 1 , further including forming the first encapsulant with an elevated portion in a periphery of the first encapsulant to reduce warpage.
4. The method of claim 1 , further including:
removing a portion of the first semiconductor die to expose the surface of the TSVs and to offset the surface of the TSVs with respect to a surface of the first encapsulant;
forming a gap between the first and second semiconductor die by mounting the second semiconductor die to the surface of the TSVs; and
depositing the second encapsulant in the gap between the first and second semiconductor die.
5. The method of claim 1 , wherein:
the first encapsulant has a first filler content;
the second encapsulant has a second filler content greater than the first filler content; and
the first CTE is greater than the second CTE.
6. A method of making a semiconductor device, comprising:
providing a carrier;
mounting a first semiconductor die including through silicon vias (TSVs) to the carrier;
depositing a first encapsulant having a first coefficient of thermal expansion (CTE) over the first semiconductor die;
exposing a surface of the TSVs;
mounting a second semiconductor die to the surface of the TSVs; and
depositing a second encapsulant having a second CTE over the first semiconductor die and second semiconductor die.
7. The method of claim 6 , further including forming the first and second encapsulants over and around the first and second semiconductor die with a chase mold.
8. The method of claim 6 , further including forming the first encapsulant with an elevated portion in a periphery of the first encapsulant to reduce warpage.
9. The method of claim 6 , further including:
removing a portion of the first semiconductor die to expose the surface of the TSVs and to offset the surface of the TSVs with respect to a surface of the first encapsulant;
forming a gap between the first and second semiconductor die by mounting the second semiconductor die to the surface of the TSVs; and
depositing the second encapsulant in the gap between the first and second semiconductor die.
10. The method of claim 6 , wherein:
the first encapsulant has a first filler content;
the second encapsulant has a second filler content greater than the first filler content; and
the first CTE is greater than the second CTE.
11. The method of claim 6 , wherein the carrier includes a thermally releasable layer for separating the first semiconductor die and first encapsulant from the carrier.
12. The method of claim 11 , further including forming an interconnect structure over the first semiconductor die and first encapsulant after removing the carrier.
13. A method of making a semiconductor device, comprising:
providing a carrier;
mounting a first semiconductor die over the carrier;
depositing a first encapsulant having a first coefficient of thermal expansion (CTE) over the first semiconductor die;
depositing a second encapsulant having a second CTE over the first semiconductor die and first encapsulant; and
forming an interconnect structure over the first semiconductor die and first encapsulant.
14. The method of claim 13 , further including:
removing a portion of the first semiconductor die to expose through silicon vias (TSVs) within the first semiconductor die; and
mounting a second semiconductor die to the TSVs.
15. The method of claim 13 , further including forming the first and second encapsulants over and around the first semiconductor die with a chase mold.
16. The method of claim 13 , further including forming the first encapsulant with an elevated portion in a periphery of the first encapsulant to reduce warpage.
17. The method of claim 13 , wherein the carrier includes a thermally releasable layer for separating the first semiconductor die and first encapsulant from the carrier.
18. The method of claim 14 , further including:
removing a portion of the first semiconductor die to expose the TSVs and to offset a surface of the TSVs with respect to a surface of the first encapsulant;
forming a gap between the first and second semiconductor die by mounting the second semiconductor die to the surface of the TSVs; and
depositing the second encapsulant in the gap between the first and second semiconductor die.
19. The method of claim 13 , wherein:
the first encapsulant has a first filler content;
the second encapsulant has a second filler content greater than the first filler content; and
the first CTE is greater than the second CTE.
20. A semiconductor device, comprising:
a first semiconductor die including through silicon vias (TSVs);
a first encapsulant having a first coefficient of thermal expansion (CTE) formed over the first semiconductor die;
a second semiconductor die mounted to the TSVs; and
a second encapsulant having a second CTE formed over the first semiconductor die and second semiconductor die.
21. The semiconductor device of claim 20 , wherein the first encapsulant includes an elevated portion in a periphery of the first encapsulant to reduce warpage.
22. The semiconductor device of claim 20 , further including:
a gap between the first and second semiconductor die; and
a portion of the second encapsulant disposed within the gap.
23. The semiconductor device of claim 20 , wherein:
the first encapsulant has a first filler content;
the second encapsulant has a second filler content greater than the first filler content; and
the first CTE is greater than the second CTE.
24. The semiconductor device of claim 20 , further including an interconnect structure formed over the first semiconductor die and first encapsulant.