Current-limiting layer and a current-reducing layer in a memory device
View Patent ↗A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime.
1. A memory device, comprising:
a nonvolatile memory element having a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer,
a current-reducing layer formed as a portion of the variable resistance layer; and
a current-limiting layer disposed between the variable resistance layer and one of the first electrode layer and the second electrode layer, wherein the current-limiting layer has a breakdown voltage that exceeds a breakdown voltage of the variable resistance layer.
2. The memory device of claim 1 , further comprising a current-steering element coupled to the variable resistance layer and having a first electrical resistance, wherein a resistivity of the current-limiting layer is adjusted such that an electrical resistance of the current-limiting layer is between about 75% and about 125% of the first electrical resistance of the current steering element when current is flowing from the first electrode layer to the second electrode layer.
3. The memory device of claim 1 , further comprising a current-steering element coupled to the variable resistance layer, wherein a thickness of the current-limiting layer is adjusted such that an electrical resistance of the current-limiting layer is between about 75% and about 125% of the electrical resistance of the current steering element when current is flowing from the first electrode to the second electrode.
4. The memory device of claim 1 , wherein the current-limiting layer comprises a resistive material selected from the group consisting of polysilicon, doped semiconductor materials, dielectric materials, metal nitrides, tantalum-containing materials, titanium-containing materials, silicon nitride, tantalum nitride, titanium nitride, hafnium nitride, germanium (Ge)-containing materials, gallium arsenide, and combinations thereof.
5. The memory device of claim 1 , wherein the current-reducing layer comprises a doped hafnium oxide material formed by adding a dopant, selected from the group consisting of aluminum and zirconium, into a portion of the variable resistance layer.
6. The memory device of claim 1 , wherein the current-reducing layer comprises a silicon oxide-containing layer formed by chemically treating the variable resistance layer with a chemical oxidation solution after the formation of the variable resistance layer.
7. The memory device of claim 1 , wherein the current-reducing layer comprises a silicon oxide-containing layer formed by chemically treating the variable resistance layer with a buffered cleaning solution after the formation of the variable resistance layer.
8. The memory device of claim 7 , wherein the current-reducing layer comprises a silicon oxide-containing layer formed by treating a portion or the bulk of the variable resistance layer with a plasma selected from the group consisting of an ozone-containing plasma and a nitrogen-containing plasma after the formation of the variable resistance layer.
9. The memory device of claim 1 , wherein the current-reducing layer comprises a high-k material layer between the variable resistance layer and the one of the first and the second electrode layers.
10. The memory device of claim 9 , wherein the high-k material layer comprises a material selected from the group consisting of aluminum oxide, zirconium oxide, silicon oxynitride, and combinations thereof.
11. A memory device, comprising:
a nonvolatile memory element having a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer;
a current-reducing layer formed into a portion of the variable resistance layer, wherein the variable resistance layer comprises a metal oxide material and the current-reducing layer comprises the metal oxide material and a dopant material disposed within at least a portion of the metal oxide material; and
a current-limiting layer disposed between the variable resistance layer and one of the first electrode layer and the second electrode layer,
wherein the current-limiting layer has a breakdown voltage that exceeds a breakdown voltage of the variable resistance layer.
12. The memory device of claim 11 , wherein the dopant material is a material selected from the group consisting of aluminum, zirconium, and combinations thereof.
13. A method of forming a nonvolatile memory device, comprising:
depositing a first electrode layer, a second electrode layer, and a variable resistance layer between the first electrode layer and the second electrode layer over a surface of a substrate;
forming a current-reducing layer as a part of the variable resistance layer; and
depositing a current-limiting layer between the variable resistance layer and at least one of the first electrode layer and the second electrode layer,
wherein the current-limiting layer has a breakdown voltage that exceeds a breakdown voltage of the variable resistance layer.
14. The method of claim 13 , further comprising:
forming a current-steering element coupled to the variable resistance layer, wherein the current steering element has a first electrical resistance; and
adjusting a resistivity of the current-limiting layer such that an electrical resistance of the current-limiting layer is between about 75% and about 125% of the first electrical resistance of the current steering element when current is flowing from the first electrode layer to the second electrode layer.
15. The method of claim 13 , wherein the current-reducing layer comprises a silicon oxide-material.
16. A method of forming a nonvolatile memory device having a nonvolatile memory element, comprising:
depositing a first electrode layer, a second electrode layer, and a variable resistance layer between the first electrode layer and the second electrode layer over a surface of a substrate;
forming a current-reducing layer into a portion of the variable resistance layer by adding a dopant during the deposition of the variable resistance layer; and
depositing a current-limiting layer between the variable resistance layer and at least one of the first electrode layer and the second electrode layer,
wherein the current-limiting layer has a breakdown voltage that exceeds a breakdown voltage of the variable resistance layer.
17. The method of claim 16 , wherein the dopant is a material selected from the group consisting of aluminum, zirconium, and combinations thereof.