Granted Patent B2

US 8,703,535 · App. 13/490,908 · Granted Apr 22, 2014

Abstract

Claims (31)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having only a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate;

connecting an integrated circuit die to the package substrate with an internal interconnect; and

forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone, wherein the warpage-compensation zone is capable of preventing warpage without additional support structure or additional stress-relief structure.

2. The method as claimed in claim 1 wherein providing the package substrate having the warpage-compensation zone includes providing the warpage-compensation zone with a zone size for controlling an amount of exposure of the substrate-interior layer exposed from the top substrate-cover.

3. The method as claimed in claim 1 wherein providing the package substrate includes providing the package substrate having a conductive portion in the warpage-compensation zone only for routing electrical signals along the package substrate.

4. The method as claimed in claim 1 wherein:

the integrated circuit die includes a die-perimeter wall on an outer periphery portion of the integrated circuit die; and

the warpage-compensation zone of the package substrate includes a top substrate-side coplanar with the die-perimeter wall.

5. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having only a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover and a top cover strip directly on the substrate-interior layer for controlling the exposure, with the warpage-compensation zone having the top cover strip extending straight between opposing edges of the package substrate;

connecting an integrated circuit die to the package substrate with an internal interconnect; and

forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone, wherein the warpage-compensation zone is capable of preventing warpage without additional support structure or additional stress-relief structure.

6. The method as claimed in claim 5 wherein providing the package substrate includes providing the top cover strip having a strip-width and a separation-width between instances of the top cover strip for controlling an amount of exposure of the substrate-interior layer exposed from the top substrate-cover.

7. The method as claimed in claim 5 wherein providing the package substrate includes providing the package substrate having instances of the top substrate-cover orthogonal and integrally connected to each other.

8. The method as claimed in claim 5 wherein providing the package substrate includes providing the warpage-compensation zone having a shape of a rectangular frame surrounding the top substrate-cover.

9. The method as claimed in claim 5 wherein connecting the integrated circuit die includes attaching the integrated circuit die with an outer periphery portion of the integrated circuit die directly over and overlapping the warpage-compensation zone.

10. An integrated circuit packaging comprising:

a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate;

an integrated circuit die connected to the package substrate with an internal interconnect; and

an encapsulation formed over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone, wherein the warpage-compensation zone does not include additional support structure or additional stress-relief structure.

11. The system as claimed in claim 10 wherein the warpage-compensation zone includes a zone size for controlling an amount of exposure of the substrate-interior layer exposed from the top substrate-cover.

12. The system as claimed in claim 10 wherein the package substrate includes a conductive portion only for routing electrical signals along the package substrate.

13. The system as claimed in claim 10 wherein:

the integrated circuit die includes a die-perimeter wall on an outer periphery portion of the integrated circuit die; and

the warpage-compensation zone of the package substrate includes a top substrate-side coplanar with the die-perimeter wall.

14. The system as claimed in claim 10 wherein the package substrate includes a top cover strip directly on the substrate-interior layer and in the warpage-compensation zone extending straight between opposing edges of the package substrate for controlling the exposure.

15. The system as claimed in claim 14 wherein the warpage-compensation zone of the package substrate includes the top cover strip having a strip-width and a separation-width between instances of the top cover strip for controlling an amount of exposure of the substrate-interior layer exposed from the top substrate-cover.

16. The system as claimed in claim 14 wherein the package substrate includes instances of the top substrate-cover orthogonal and integrally connected to each other.

17. The system as claimed in claim 14 wherein the top substrate-cover of the package substrate is not for providing additional support or stress-relief in the warpage-compensation zone.

18. The system as claimed in claim 14 wherein an outer periphery portion of the integrated circuit die is directly over and overlaps the warpage-compensation zone.

Assignments (6)