Integrated circuit packaging system with through silicon via and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a bottom integrated circuit having bottom through silicon vias with a bottom via pitch;

mounting outer interconnects over the bottom integrated circuit;

mounting a top integrated circuit between the outer interconnects, the top integrated circuit having top through silicon vias with a top via pitch less than the bottom via pitch; and

forming a package encapsulation having a top mold surface coplanar with a chip top surface of the top integrated circuit.

2. The method as claimed in claim 1 wherein mounting the outer interconnects includes mounting the outer interconnects having an outer interconnect pitch greater than the top via pitch.

3. The method as claimed in claim 1 wherein forming the package encapsulation includes having the top mold surface coplanar with a top interconnect surface of the outer interconnect.

4. The method as claimed in claim 1 wherein mounting the top integrated circuit includes mounting the top integrated circuit with top interconnects having a top interconnect pitch equal to the top via pitch.

5. A method of manufacture of an integrated circuit packaging system comprising:

providing a bottom integrated circuit having bottom through silicon vias with a bottom via pitch;

mounting outer interconnects over the bottom integrated circuit;

mounting a top integrated circuit between the outer interconnects, the top integrated circuit having top through silicon vias with a top via pitch less than the bottom via pitch; and

forming a package encapsulation having a top mold surface coplanar with a chip top surface of the for integrated circuit, the package encapsulation over the bottom integrated circuit, the outer interconnects, and the top integrated circuit.

6. The method as claimed in claim 5 wherein:

mounting the top integrated circuit includes mounting the top integrated circuit with top interconnects over the bottom integrated circuit, the top interconnects having a top interconnect pitch less than the bottom via pitch; and

further comprising:

mounting a top package over the top integrated circuit.

7. The method as claimed in claim 5 further comprising:

forming a bottom package having a bottom external connector and the package encapsulation; and

mounting a top package having a top outer external connector over the bottom package, the top outer external connector non-horizontally aligned with the outer interconnect, the bottom through silicon via, and the bottom external connector.

8. The method as claimed in claim 5 further comprising:

forming a bottom package having a bottom external connector and the top integrated circuit with a top interconnect; and

mounting a top package having a top inner external connector over the bottom package, the top inner external connector non-horizontally aligned with the top through silicon via and the top interconnect.

9. The method as claimed in claim 5 further comprising:

providing a package carrier; and

forming a bottom package with the top integrated circuit and the bottom integrated circuit, the top integrated circuit and the bottom integrated circuit over the package carrier.

10. An integrated circuit packaging system comprising:

a bottom integrated circuit having bottom through silicon vias with a bottom via pitch;

outer interconnects over the bottom integrated circuit:

a top integrated circuit between the outer interconnects, the top integrated circuit having to through silicon vias with a top via pitch less than the bottom via pitch; and

a package encapsulation having a top mold surface coplanar with a chip top surface of the top integrated circuit.

11. The system as claimed in claim 10 wherein the outer interconnects includes the outer interconnects having an outer interconnect pitch greater than the top via pitch.

12. The system as claimed in claim 10 wherein the top mold surface of the package encapsulation is coplanar with a top interconnect surface of the outer interconnect.

13. The system as claimed in claim 10 wherein the top integrated circuit includes the top integrated circuit with top interconnects having a top interconnect pitch equal to the top via pitch.

14. The system as claimed in claim 10 wherein the package encapsulation is over the bottom integrated circuit, the outer interconnects, and the top integrated circuit.

15. The system as claimed in claim 14 wherein:

the top integrated circuit includes the top integrated circuit with top interconnects over the bottom integrated circuit, the top interconnects having a top interconnect pitch less than the bottom via pitch; and

further comprising:

a top package over the top integrated circuit.

16. The system as claimed in claim 14 further comprising:

a bottom package having a bottom external connector and the package encapsulation; and

a top package having a top outer external connector over the bottom package, the top outer external connector non-horizontally aligned with the outer interconnect, the bottom through silicon via, and the bottom external connector.

17. The system as claimed in claim 14 further comprising:

a bottom package having a bottom external connector and the top integrated circuit with a top interconnect; and

a top package having a top inner external connector over the bottom package, the top inner external connector non-horizontally aligned with the top through silicon via and the top interconnect.

18. The system as claimed in claim 14 further comprising:

a package carrier; and

a bottom package with the top integrated circuit and the bottom integrated circuit, the top integrated circuit and the bottom integrated circuit over the package carrier.