RF power multi-chip module package
High power multi-chip module packages for packaging semiconductor dice are disclosed. The disclosed packages have an output power of at least 1 kilowatt (kW) and can have an operating signal frequency in a range of hundreds of MHz. The high power multi-chip module packages have base plates with multiple planes or layers that can be conductive and may be thin metal layers in some examples. The multiple planes are formed and overlaid in such a way that they help reduce stray inductance values caused by the packaging itself, which improves overall device operation and efficiency. Current loops created when one of the multi-chip modules is in a turn-on condition are balanced and opposed and generate a minimized B-Field that is restricted by the manner in which the multiples planes of the base plate are overlaid, thus reducing the stray inductance values and improving device operation.
1. A base plate for a high power multi-chip module package having a power output of at least 1 kilowatt (kW) and an operating signal frequency in the range of up to hundreds of MHz, comprising:
a low side switch (LSS) plane having an LSS protrusion;
a positive supply voltage (PSV) plane having a first recession and a second recession, the first recession configured to receive the LSS protrusion and cause the LSS plane and the PSV plane to be intermingled; and
a high side switch (HSS) plane, a portion of the HSS plane placed over a portion of the PSV plane, the HSS plane having an HSS protrusion structured to intermingle with the second recession of the PSV plane, the HSS plane placed over the portion of the PSV plane to define an HSS-PSV plane edge; and
an open gap defined between an intermingled edge of the LSS plane and the HSS-PSV plane edge;
wherein at a turn-on condition for multiple transistor dies mounted to the base plate, transistor die driver current loops are created by currents flowing between the multiple transistor dies and respective multiple transistor die drivers that are balanced and opposed, and output current loops are created by currents flowing from the multiple transistor dies to an output destination that are also balanced and opposed.
2. The base plate of claim 1 , wherein the LSS plane and the PSV plane are co-planar.
3. The base plate of claim 1 , wherein the LSS plane, the PSV plane, and the HSS plane are all conductive.
4. The base plate of claim 1 , wherein the LSS plane, the PSV plane, and the HSS plane are all thin metal layers.
5. The base plate of claim 1 , wherein the transistor die driver currents generate a U-shaped transistor die driver current B-Field that is restricted to the open gap.
6. The base plate of claim 1 , further comprising an insulator placed between the PSV plane and the HSS plane.
7. The base plate of claim 6 , wherein the insulator includes a glass overlay.
8. The base plate of claim 1 , wherein the HSS plane includes a cut-out and the cut-out is placed over the portion of the PSV plane.
9. The base plate of claim 1 , wherein, at the turn-on condition, a shunt capacitor current loop is created by a current flowing from a shunt capacitor that maintains constant voltage between the multiple transistor dies to one of the multiple transistor dies, the shunt capacitor current loop surrounding the entire open gap, and the shunt capacitor current loop generating a shunt capacitor B-field restricted to the open gap.
10. A high power multi-chip module package having a power output of at least 1 kilowatt (kW) and an operating signal frequency in a range of up to hundreds of MHz, comprising:
a base plate having:
a low side switch (LSS) plane having an LSS protrusion;
a positive supply voltage (PSV) plane having a first recession and a second recession, the first recession configured to receive the LSS protrusion and cause the LSS plane and the PSV plane to intermingle; and
a high side switch (HSS) plane, a portion of the HSS plane placed over a portion of the PSV plane, the HSS plane having an HSS protrusion structured to intermingle with the second recession of the PSV plane, the HSS plane placed over the portion of the PSV plane to define an HSS-PSV plane edge; and
an open gap defined between an intermingled edge of the LSS plane and the HSS-PSV plane edge;
a high side switch and a high side driver electrically connected together, the high side switch mounted on the PSV plane and the high side driver mounted on the HSS plane;
a low side switch and a low side driver electrically connected together, the low side switch mounted on the HSS plane and the low side driver mounted on the LSS plane; and
a shunt capacitor arranged to electrically connect the PSV plane and the LSS plane and maintain a constant voltage between the high side switch and the low side switch;
wherein, at a turn-on condition for either the high side switch or the low side switch, driver current loops are created by current flowing between the high side switch or the low side switch, whichever is in the turn-on condition, and the respective high side driver or low side driver, the driver current loops being balanced and opposed,
and wherein, at the turn-on condition for either the high side switch or the low side switch, output current loops are created by currents flowing from the high side switch or the low side switch, whichever is in the turn-on condition, to an output destination, the output current loops being balanced and opposed.
11. The high power multi-chip module package of claim 10 , wherein the LSS plane and the PSV plane are co-planar.
12. The high power multi-chip module package of claim 10 , wherein the LSS plane, the PSV plane, and the HSS plane are all conductive.
13. The high power multi-chip module package of claim 10 , wherein the LSS plane, the PSV plane, and the HSS plane are all thin metal layers.
14. The high power multi-chip module package of claim 10 , wherein the transistor die driver currents generate a U-shaped transistor die driver current B-Field that is restricted to the open gap.
15. The high power multi-chip module package of claim 10 , further comprising an insulator placed between the PSV plane and the HSS plane.
16. The high power multi-chip module package of claim 15 , wherein the insulator includes a glass overlay.
17. The high power multi-chip module package of claim 10 , wherein the HSS plane includes a cut-out and the cut-out is placed over the portion of the PSV plane.
18. The high power multi-chip module package of claim 10 , wherein, at the turn-on condition, a shunt capacitor current loop is created by a current flowing from the shunt capacitor to the first switch or the second switch, the shunt capacitor current loop surrounding the entire open gap, and the shunt capacitor current loop generating a shunt capacitor B-field restricted to the open gap.