Granted Patent B2

US 9,696,213 · App. 14/199,082 · Granted Jul 4, 2017

Abstract

Claims (53)

1. A temperature sensor comprising:

a voltage generating part generating (2 N −1)-midpoint voltages (N is a natural number equal to or larger than 2) based on a reference voltage which does not depend on a temperature;

a sense part generating a temperature sensing voltage which depends on the temperature; and

an arithmetic part comprising comparator, multiplexer and latch circuit configured to generate N-bit temperature data by carrying out first to N-th operations each comparing the temperature sensing voltage with one of the (2 N −1)-midpoint voltages.

2. The sensor of claim 1 ,

wherein the first operation decides a most significant bit of the N-bit temperature data, and the second operation decides a least significant bit of the N-bit temperature data.

3. The sensor of claim 1 ,

wherein the first to N-th operations are carried out in series.

4. The sensor of claim 3 ,

wherein the arithmetic part comprises first to N-th logic circuits, and

each of the first to N-th logic circuits comprises a comparator which compares the temperature sensing voltage with one of the (2 N −1)-midpoint voltages, and a latch circuit which latches an output signal of the comparator.

5. The sensor of claim 4 ,

wherein the latch circuit latches one bit of the N-bit temperature data.

6. The sensor of claim 4 ,

wherein an i-th logic circuit (i is one of 1 to N−1) comprises the multiplexer which selects one of the (2 N −1)-midpoint voltages based on one bit latched in the latch circuit in the i-th logic circuit, and one of the (2 N −1)-midpoint voltages selected by the multiplexer is inputted in the comparator in the (i+1)-th logic circuit.

7. The sensor of claim 4 ,

wherein the arithmetic part is configured to:

generate N-bit temperature data by carrying out (N+1)-th to 2N-th operations each comparing the temperature sensing voltage with one of the (2 N -1)-midpoint voltages, and

generate a real temperature by calculating an average of N-bit temperature data generated by the first to N-th operations and N-bit temperature data generated by the (N+1)-th to 2N-th operations.

8. The sensor of claim 7

wherein the comparator comprises a non-inverting input terminal and an inverting input terminal, and

one of the (2 N −1)-midpoint voltages is inputted in the inverting input terminal of the comparator in the first to N-th operations, and is inputted in the non-inverting input terminal of the comparator in the (N+1)-th to 2N-th operations.

9. The sensor of claim 3 ,

wherein the comparator compares the temperature sensing voltage with one of the (2 N −1)-midpoint voltages, and the latch circuit latches an output signal of the comparator.

10. The sensor of claim 9 ,

wherein the first to N-th operations are carried out by reusing the comparator repeatedly.

11. The sensor of claim 9 ,

wherein the latch circuit latches one bit of the N-bit temperature data.

12. The sensor of claim 9 ,

wherein the multiplexer selects one of the (2 N −1)-midpoint voltages based on one bit latched in the latch circuit in the i-th operation (i is one of 1 to N−1), and one of the (2 N −1)-midpoint voltages selected by the multiplexer is inputted in the comparator in the (i+1)-th operation.

13. The sensor of claim 9 ,

wherein the arithmetic part is configured to:

generate N-bit temperature data by carrying out (N+1)-th to 2N-th operations each comparing the temperature sensing voltage with one of the (2 N −1)-midpoint voltages, and

generate a real temperature by calculating an average of N-bit temperature data generated by the first to N-th operations and N-bit temperature data generated by the (N+1)-th to 2N-th operations.

14. The sensor of claim 13 ,

wherein the comparator comprises a non-inverting input terminal and an inverting input terminal, and

one of the (2 N −1)-midpoint voltages is inputted in the inverting input terminal of the comparator in the first to N-th operations, and is inputted in the non-inverting input terminal of the comparator in the (N+1)-th to 2N-th operations.

15. The sensor of claim 1 ,

wherein at least two operations of the first to N-th operations are executed in parallel.

16. The sensor of claim 15 ,

wherein when a number of the at least two operations is two, the arithmetic part comprises three comparators which compare the temperature sensing voltage with one of the (2 N −1)-midpoint voltages respectively, and three latch circuits which latch output signals of the three comparator respectively.

17. The sensor of claim 16 ,

wherein two of the three latch circuits latch two bits of the N-bit temperature data.

18. The sensor of claim 16 ,

wherein the first to N-th operations are carried out by reusing the three comparators repeatedly.

19. The sensor of claim 16 ,

wherein the arithmetic part is configured to:

generate N-bit temperature data by carrying out (N+1)-th to 2N-th operations each comparing the temperature sensing voltage with one of the (2 N −1)-midpoint voltages, and

generate a real temperature by calculating an average of N-bit temperature data generated by the first to N-th operations and N-bit temperature data generated by the (N+1)-th to 2N-th operations.

20. The sensor of claim 19 ,

wherein the comparator comprises a non-inverting input terminal and an inverting input terminal, and

one of the (2 N −1)-midpoint voltages is inputted in the inverting input terminal of the comparator in the first to N-th operations, and is inputted in the non-inverting input terminal of the comparator in the (N+1)-th to 2N-th operations.

21. A LSI chip comprising the sensor of claim 1 , the sensor detecting a real temperature of the LSI chip.

Assignments (8)