Randomizing current injection circuit to obscure gate noise for added security
A circuit for obscuring gate switching noise includes a synchronous clock source; an asynchronous clock source; at least one current source; and a random number generating circuit for receiving clock inputs from the synchronous clock source and the asynchronous clock source, the random number generating circuit generating randomly changing asynchronous digital control signals for controlling the current source.
1. A circuit for obscuring gate switching noise, comprising:
a synchronous clock source;
an asynchronous clock source;
a plurality of current sources;
a random number generating circuit receiving clock inputs from the synchronous clock source and the asynchronous clock source, the random number generating circuit generating randomly changing asynchronous digital control signals, and
a bitstream buffer receiving the asynchronous digital control signals and controlling an amplitude of current from the plurality of current sources, wherein the bitstream buffer comprises an input and a plurality of outputs, wherein each output has a predefined offset with respect to a stored bitstream and wherein each current source is coupled with a different one of said plurality of outputs.
2. A circuit in accordance with claim 1 , wherein the synchronous clock sources comprises a system clock.
3. A circuit in accordance with claim 1 , wherein each current source is a constant current source.
4. A circuit in accordance with claim 3 , wherein each constant current source comprises a current mirror comprising a first bipolar transistor whose load path is coupled between a power supply and ground through a resistor and a second bipolar transistor whose load path is coupled between a control input of the first bipolar transistor and ground and whose control input is connected to a node between the load path of the first bipolar transistor and the resistor.
5. A circuit in accordance with claim 1 , the synchronous clock source comprising an external clock source.
6. A circuit in accordance with claim 1 , the asynchronous clock source comprising an internal clock source.
7. A method for providing a circuit for obscuring gate switching noise, comprising:
providing a synchronous clock source;
providing an asynchronous clock source;
providing a plurality of current sources; and
receiving clock inputs from the synchronous clock source and from the asynchronous clock source by a random number generating circuit,
generating randomly changing asynchronous digital control signals by the random number generating circuit, and
feeding an output signal of the random number generating circuit into a bitstream buffer and controlling an amplitude of the plurality of current sources, wherein the plurality of current sources tap from different bit offsets in the bitstream buffer.
8. A method in accordance with claim 7 , wherein the synchronous clock sources comprises a system clock.
9. A method in accordance with claim 7 , wherein the synchronous clock source comprises an external clock source.
10. A method in accordance with claim 7 , the asynchronous clock source comprising an internal clock source.
11. A method according to claim 7 , wherein each current source of the plurality of current sources is a constant current source.
12. A method according to claim 7 , wherein the method is performed within an integrated encryption device comprising an encryption encoder and where the method obscures gate switching noise of the integrated encryption device.
13. An integrated circuit, comprising:
an encryption processor; and
a circuit for obscuring gate switching noise, comprising:
a synchronous clock source;
an asynchronous clock source;
a plurality of current sources;
a random number generating circuit receiving clock inputs from the synchronous clock source and the asynchronous clock source, the random number generating circuit generating randomly changing asynchronous digital control signals, and
a bitstream buffer receiving an output signal of the random number generating circuit and being configured to control an amplitude of the plurality of current sources, wherein the plurality of current sources tap from different bit offsets in the bitstream buffer.
14. An integrated circuit in accordance with claim 13 , wherein the synchronous clock sources comprises a system clock.
15. An integrated circuit in accordance with claim 13 , the synchronous clock source comprising an external clock source.
16. An integrated circuit in accordance with claim 13 , the asynchronous clock source comprising an internal clock source.
17. An integrated circuit in accordance with claim 13 , the encryption processor comprising a code hopping encryption processor.
18. An integrated circuit in accordance with claim 13 , wherein each current source of the plurality of current sources is a constant current source.
19. An integrated circuit in accordance with claim 18 , wherein each constant current source comprises a current mirror comprising a first bipolar transistor whose load path is coupled between a power supply and ground through a resistor and a second bipolar transistor whose load path is coupled between a control input of the first bipolar transistor and ground and whose control input is connected to a node between the load path of the first bipolar transistor and the resistor.
20. A circuit for obscuring gate switching noise, comprising:
a synchronous clock source;
an asynchronous clock source;
at least one constant current source; and
a random number generating circuit receiving clock inputs from the synchronous clock source and the asynchronous clock source, the random number generating circuit generating randomly changing asynchronous digital control signals for controlling the current source, wherein the constant current source comprises a current mirror comprising a first bipolar transistor whose load path is coupled between a power supply and ground through a resistor and a second bipolar transistor whose load path is coupled between a control input of the first bipolar transistor and ground and whose control input is connected to a node between the load path of the first bipolar transistor and the resistor.